Vertical memory device

Patent metadata

Field	Value
Publication number	US-11024642-B2
Application number	US-201916508727-A
Country	US
Kind code	B2
Filing date	Jul 11, 2019
Priority date	Dec 19, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A vertical memory device includes a stacked structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers extending in a direction perpendicular to an upper surface of the substrate on a first side surface of the stacked structure and spaced apart from each other in a direction parallel to the upper surface of the substrate, and a common source layer disposed between the stacked structure and the substrate and contacting the channel layers.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a stacked structure comprising a plurality of gate electrode layers including a polycrystalline silicon stacked on a substrate;
a plurality of channel layers extending in a direction perpendicular to an upper surface of the substrate on a first side surface of the stacked structure, and spaced apart from each other in a direction parallel to the upper surface of the substrate;
a common source layer disposed between the stacked structure and the substrate and contacting a portion of sidewalls of the channel layers;
a gate insulating layer disposed between the stacked structure and the channel layers and covering at least a portion of the first side surface of the stacked structure;
a plurality of cutting insulating layers disposed alternately with the channel layers on the first side surface of the stacked structure; and
a separation pattern disposed on a second side surface of the stacked structure,
wherein the second side surface opposes the first side surface, and
wherein the common source layer penetrates through the gate insulating layer and contacts the channel layers.

2. The vertical memory device of claim 1 , wherein the gate insulating layer is disposed between the channel layers and the substrate, and wherein the channel layers and the substrate are electrically connected by the common source layer.

3. The vertical memory device of claim 1 ,
wherein the separation pattern comprises an insulating layer.

4. The vertical memory device of claim 1 , wherein the common source layer comprises a first portion in contact with lower ends of the channel layers, and second portions intersecting the first portion.

5. The vertical memory device of claim 1 , wherein the common source layer comprises p-type polycrystalline silicon.

6. The vertical memory device of claim 1 , wherein the gate electrode layers comprise p-type polycrystalline silicon, and the common source layer comprises n-type polycrystalline silicon.

7. A vertical memory device, comprising:
a plurality of separation patterns disposed on a substrate and spaced apart from each other, wherein the separation patterns extend in a first direction parallel to an upper surface of the substrate;
a first stacked structure and a second stacked structure below the first stacked structure, disposed between the separation patterns and extending in the first direction, wherein the first stacked structure and the second stacked structure each comprise a plurality of gate electrode layers;
a plurality of first channel layers disposed on a side surface of the first stacked structure;
a plurality of second channel layers disposed on a side surface of the second stacked structure and facing the first channel layers;
a common source layer disposed between the substrate and at least one of the first stacked structure and the second stacked structure, and electrically connected to the first channel layers and the second channel layers;
a plurality of gap fill insulating layers disposed between the first channel layers and the second channel layers; and
a plurality of cutting insulating layers alternately disposed with the gap fill insulating layers in the first direction, and disposed between the first stacked structure and the second stacked structure,
wherein the cutting insulating layers are in contact with the common source layer, the first channel layers and the second channel layers, and
wherein the separation patterns penetrate through the common source layer.

8. The vertical memory device of claim 7 , wherein the common source layer comprises a first common source layer disposed between the first stacked structure and the substrate, and a second common source layer disposed between the second stacked structure and the substrate.

9. The vertical memory device of claim 8 , further comprising:
a plurality of gate insulating layers disposed between the first stacked structure and the first channel layers, and disposed between the second stacked structure and the second channel layers,
wherein the first common source layer and the second common source layer penetrate through the gate insulating layers and contact the first channel layers and the second channel layers, respectively.

10. The vertical memory device of claim 7 , wherein the gate electrode layers and the common source layer comprise p-type polycrystalline silicon.

11. The vertical memory device of claim 7 , wherein the gate electrode layers comprise p-type polycrystalline silicon, and the common source layer comprises n-type polycrystalline silicon.

12. A vertical memory device, comprising:
a stacked structure stacked on a substrate and comprising a plurality of conductive layers disposed above an upper surface of the substrate and extending in a direction parallel to the upper surface of the substrate; and
a plurality of channel layers extending in a direction perpendicular to the upper surface of the substrate, disposed on a side surface of the stacked structure, and spaced apart from each other; and
a gate insulating layer disposed between the stacked structure and the plurality of channel layers and covering at least a portion of the first side surface of the stacked structure,
wherein the plurality of conductive layers comprises a first conductive layer insulated from the channel layers and a second conductive layer in contact with the channel layers,
wherein the second conductive layer comprises a first portion in contact with lower ends of the channel layers and a plurality of second portions intersecting the first portion.

13. The vertical memory device of claim 12 , wherein the plurality of conductive layers further comprises an intermediate conductive layer,
wherein the first conductive layer includes a plurality of upper conductive layers disposed on the intermediate conductive layer and a plurality of lower conductive layers disposed below the intermediate conductive layer,
wherein the stacked structure comprises an upper stacked structure comprising the upper conductive layers, and a lower stacked structure comprising the lower conductive layers,
wherein the channel layers comprise a plurality of upper channel layers disposed on a side surface of the upper stacked structure and a plurality of lower channel layers disposed on a side surface of the lower stacked structure, and
wherein lower portions of the upper channel layers and upper portions of the lower channel layers contact the intermediate conductive layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kyung Hwan
• Kim Yong Seok
• Lim Jun Hee
• Kanamori Kohji

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title