Manufacturing method of semiconductor device including multi-layered source layer and channel extending therethrough

Patent metadata

Field	Value
Publication number	US-9978771-B2
Application number	US-201615350564-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	Jun 30, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

There are provided a manufacturing method of a semiconductor device. A manufacturing method of a semiconductor device includes forming a preliminary source stack structure including a first source layer, a first protective layer, a sacrificial layer, a second protective layer, and a second source layer, which are sequentially stacked in the recited order, forming channel layers extending through the second source layer and partially inside the first source layer, and growing a first region of an interlayer source layer from each channel layer, the first region of the interlayer source layer surrounding each channel layer in a region between the first and second protective layers.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming a preliminary source stack structure including a first source layer, a first protective layer, a sacrificial layer, a second protective layer, and a second source layer, which are sequentially stacked in the recited order;
forming channel layers extending through the second source layer and partially inside the first source layer; and
growing a first region of an interlayer source layer from each channel layer, the first region of the interlayer source layer surrounding each channel layer in a region between the first and second protective layers.

2. The method of claim 1 , wherein the growing of the first region of the interlayer source layer further comprises:
surrounding each of the channel layers with a multi-layered layer;
forming, between the channel layers, a source penetration hole penetrating the second source layer and the second protective layer, the source penetration hole exposing the sacrificial layer therethrough;
removing the sacrificial layer exposed through the source penetration hole, thereby forming a first opening between the first and second protective layers;
removing the multi-layered layer exposed through the first opening, thereby forming a second opening exposing the channel layers therethrough; and
growing the first region of the interlayer source layer from each of the channel layers exposed through the second opening.

3. The method of claim 2 , further comprising:
removing the first and second protective layers exposed through the first opening, thereby forming a third opening between the first and second source layers; and
growing a second region of the interlayer source layer from the first and second source layers exposed through the first and third openings, and the first region of the interlayer source layer.

4. The method of claim 2 , further comprising:
removing the first and second protective layers exposed through the first opening, thereby forming a third opening between the first and second source layers; and
forming, through a coating process, a second region of the interlayer source layer between the first region and the first source layer exposed through the first and third openings, and between the first region and the second source layer exposed through the first and third openings.

5. The method of claim 2 , wherein the first and second protective layers remain during the forming of the second opening, thereby blocking the first and second source layers during the forming of the first region of the interlayer source layer.

6. The method of claim 2 , wherein the multi-layered layer includes a tunnel insulating layer surrounding each of the channel layers, a data storage layer surrounding the tunnel insulating layer, and a blocking insulating layer surrounding the data storage layer.

7. The method of claim 6 , wherein each of the first protective layer and the second protective layer includes:
a first sub-protective layer having a different etching selection ratio from the tunnel insulating layer;
a second sub-protective layer having a different etching selection ratio from the data storage layer; and
a third sub-protective layer having a different etching selection ratio from the blocking insulating layer.

8. The method of claim 2 , further comprising forming, on a sidewall of the source penetration hole, a sidewall insulating layer including the same material as the first protective layer or the second protective layer.

9. The method of claim 8 , wherein the sidewall insulating layer is removed after the growing of the first region of the interlayer source layer.

10. The method of claim 2 , further comprising, before the forming of the channel layers, alternately stacking first material layers and second material layers on the second source layer,
wherein the channel layers are formed to penetrate the first material layers and the second material layers, and
wherein the method further comprises, before the forming of the source penetration hole, forming a slit penetrating the first material layers and the second material layers between the channel layers.

11. The method of claim 10 , further comprising, before the forming of the source penetration hole, replacing the first material layers or the second material layers with a third material layer through the slit.

12. The method of claim 1 , wherein the sacrificial layer is formed of a material having a different etching selection ratio from the first and second source layers.

13. The method of claim 1 , wherein each of the first protective layer and the second protective layer has a first sub-protective layer including a nitride layer, a second sub-protective layer disposed on the first sub-protective layer, the second sub-protective layer including an oxide layer, and a third sub-protective layer disposed on the second sub-protective layer, the third sub-protective layer including a nitride layer.

14. The method of claim 1 , wherein the first and second protective layers are formed of a material having a different etching selection ratio from the first source layer, the sacrificial layer, and the second source layer, and are removed after the growing of the first region of the interlayer source layer.

Assignees

• Sk Hynix Inc

Inventors

• Hwang Sun Kak

Classifications

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/76843

  Electricity · mapped topic

• H01L21/76879

  Electricity · mapped topic