Memory apparatus and method of controlling memory apparatus

Patent metadata

Field	Value
Publication number	US-11024376-B2
Application number	US-201816612458-A
Country	US
Kind code	B2
Filing date	May 11, 2018
Priority date	May 19, 2017
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.

First claim

The invention claimed is:

1. A memory apparatus, comprising:
a memory cell at an intersection of a first wiring line and a second wiring line, wherein
the memory cell includes a variable resistor and a selector, and
the variable resistor has a resistance state that changes to a first resistance state and a second resistance state; and

a drive circuit configured to:
write data to the memory cell based on change of the resistance state of the variable resistor from the first resistance state to the second resistance state;
erase the data in the memory cell based on change of the resistance state of the variable resistor from the second resistance state to the first resistance state;
change, at a time of the erase of the data, a voltage to the memory cell from a first voltage to a second voltage in a stepwise manner; and
change, at the time of the erase of the data, a current limit value from a first current value to a second current value in the stepwise manner, wherein
the current limit value limits a magnitude of a current through the memory cell;
a value of a voltage to the variable resistor is within a specific voltage range based on the current limit value that is the second current value, and
the current limit value is changed to the second current value in a period in which the voltage of the memory cell is the second voltage.

2. The memory apparatus according to claim 1 , wherein, at the time of the erase of the data, the drive circuit is further configured to:
increase the voltage to the memory cell in the stepwise manner; and
decrease the current limit value in the stepwise manner.

3. The memory apparatus according to claim 2 , wherein
at the time of the erase of the data, the drive circuit is further configured to apply the first voltage to the memory cell, and then apply the second voltage to the memory cell,
the second voltage is larger than the first voltage,
the selector is in a selected state based on the voltage to the memory cell is the first voltage and the variable resistor is in the second resistance state, and
the selector is in the selected state based on the voltage to the memory cell is the second voltage and the variable resistor is in the first resistance state.

4. The memory apparatus according to claim 3 , wherein the drive circuit is further configured to:
set the current limit value to the first current value for the change of the resistance state of the variable resistor from the second resistance state to the first resistance state, wherein
the current limit value is set to the first current value in a period in which an erase current flows in the memory cell, and
the current limit value is set to the first current value based on the voltage of the memory cell is the first voltage; and

set the current limit value to the second current value in the period in which the voltage of the memory cell is the second voltage, wherein the second current value is less than the first current value.

5. The memory apparatus according to claim 4 , wherein the specific voltage range corresponds to a range between a value of a voltage to the selector while the voltage to the memory cell is the first voltage at the time of the erase of the data and the value of the voltage to the variable resistor while the first voltage to the memory cell is the first voltage at the time of the erase of the data.

6. The memory apparatus according to claim 1 , wherein
at the time of the erase of the data, the drive circuit is further configured to apply the first voltage to the memory cell, and then apply the second voltage to the memory cell,
the selector is in a selected state based on the voltage to the memory cell is the first voltage and the variable resistor is in the second resistance state, and
the second voltage is lower than the first voltage.

7. The memory apparatus according to claim 6 , wherein the drive circuit is further configured to:
set the current limit value to the first current value to maintain the resistance state of the variable resistor in the second resistance state, wherein
the current limit value is set to the first current value at a time point in which the selector changes from a non-selected state to the selected state, and
the current limit value is set to the first current value based on the voltage of the memory cell is the first voltage; and

set the current limit value to the second current value in the period in which the voltage of the memory cell is the second voltage, wherein the second current value is greater than the first current value.

8. The memory apparatus according to claim 7 , wherein the specific voltage range corresponds to a range between a value of a voltage to the selector while the first voltage to the memory cell is the first voltage at the time of the erase of the data and the value of the voltage to the variable resistor while the voltage to the memory cell is the first voltage at the time of the erase of the data.

9. The memory apparatus according to claim 5 , further comprising:
a current detection circuit configured to detect the current through the memory cell; and
a determination unit configured to:
multiply a value of the detected current by a resistance value of the memory cell;
obtain the value of the voltage to the variable resistor; and
determine that the obtained voltage value is within the specific voltage range.

10. A method of controlling a memory apparatus, the method comprising:
writing, by a drive circuit, data to a memory cell based on change of a resistance state of a variable resistor from a first resistance state to a second resistance state;
erasing, by the drive circuit, the data in the memory cell based on change of the resistance state of the variable resistor from the second resistance state to the first resistance state;
changing, by the drive circuit, at a time of the erase of the data, a voltage to the memory cell from a first voltage to a second voltage in a stepwise manner; and
changing, by the drive circuit, at the time of the erase of the data, a current limit value from a first current value to a second current value in the stepwise manner, wherein
the current limit value limits a magnitude of a current flowing through the memory cell,
a value of a voltage to the variable resistor is within a specific voltage range based on the current limit value is the second current value,
the current limit value is changed to the second current value in a period in which the voltage of the memory cell is the second voltage,
the memory cell is at an intersection of a first wiring line and a second wiring line,
the memory cell includes the variable resistor and a selector, and
the variable resistor has the resistance state that changes to the first resistance state and the second resistance state.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Mori Yotaro
• Kitagawa Makoto
• Okuno Jun
• Terada Haruhiko

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/003 Primary

  Cell access · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0097 Primary

  Erasing, e.g. resetting, circuits or methods · CPC title