Non-volatile memory device and method of controlling non-volatile memory device

Patent metadata

Field	Value
Publication number	US-10706925-B2
Application number	US-201515516542-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Nov 6, 2014
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A non-volatile memory device of the disclosure includes a memory cell, a writing circuit, and a current controller. The memory cell is disposed at an intersection of a first wiring and a second wiring, and includes a variable resistance element having a resistance state that is variable between a first resistance state and a second resistance state. The writing circuit varies the variable resistance element from the first resistance state to the second resistance state, and thereby performs writing of data on the memory cell. The current controller controls a current and thereby limits the current to a predetermined limit current value. The current is caused to flow through the first wiring or the second wiring by the writing circuit upon performing of the writing of the data. The current controller causes the predetermined limit current value to be a first limit current value in a period before a time at which the variable resistance element is varied to the second resistance state, and varies the predetermined limit current value from the first limit current value to a second limit current value after the time at which the variable resistance element is varied to the second resistance state.

First claim

The invention claimed is:

1. A non-volatile memory device comprising:
a writing circuit configured to:
perform a writing operation that writes data onto a memory cell by varying a resistance state of a variable resistance element from a first resistance state to a second resistance state; and

a current controller configured to:
perform, before the writing circuit performs the writing operation, a first current-limiting operation that limits current flowing through the memory cell to a first limit current value, and
perform, after the writing circuit performs the writing operation, a second current-limiting operation that varies the current flowing through the memory cell from the first limit current value to a second limit current value.

2. The non-volatile memory device according to claim 1 , further comprising:
the memory cell, the memory cell comprises the variable resistance element.

3. The non-volatile memory device according to claim 1 , wherein the resistance state of the variable resistance element is higher in the first resistance state than in the second resistance state.

4. The non-volatile memory device according to claim 1 , wherein the current controller is configured to perform the first current-limiting operation in a manner that sets the current flowing through the memory cell to the first limit current value.

5. The non-volatile memory device according to claim 1 , wherein the second current-limiting operation limits the current flowing through the memory cell to the second limit current value.

6. The non-volatile memory device according to claim 1 , wherein the second limit current value is higher than the first limit current value.

7. The non-volatile memory device according to claim 1 , wherein the current controller is configured to perform the second current-limiting operation in a manner that sets the current flowing through the memory cell to the second limit current value.

8. The non-volatile memory device according to claim 1 , wherein the current controller is electrically connected to the writing circuit.

9. The non-volatile memory device according to claim 1 , wherein the memory cell is disposed at an intersection of a first wiring and a second wiring.

10. The non-volatile memory device according to claim 9 , wherein the first wiring and the second wiring are electrically connected to the memory cell.

11. The non-volatile memory device according to claim 9 , wherein the writing circuit is configured to change the resistance state of the variable resistance element from the first resistance state to the second resistance state by driving the first wiring to a predetermined voltage.

12. The non-volatile memory device according to claim 11 , wherein the first wiring is a bit line in a memory cell array when the second wiring is a word line in the memory cell array.

13. The non-volatile memory device according to claim 12 , wherein the second wiring is the bit line when the first wiring is the word line.

14. The non-volatile memory device according to claim 13 , wherein the current controller is configured to detect whether or not a bit line current is higher than a reference current, the bit line current is current that is present on the bit line.

15. The non-volatile memory device according to claim 12 , wherein the memory cell array comprises an array of memory cells, the memory cell is one of the memory cells in the array.

16. A method of controlling a non-volatile memory device, the method comprising:
performing, by a current controller before a writing circuit performs a writing operation, a first current-limiting operation in a manner that limits current flowing through a memory cell to a first limit current value;
performing, by the writing circuit to write data onto the memory cell, a writing operation in a manner that varies a resistance state of a variable resistance element from a first resistance state to a second resistance state; and
performing, by the current controller after the writing circuit performs the writing operation, a second current-limiting operation in a manner that varies the current flowing through the memory cell from the first limit current value to a second limit current value.

17. The method according to claim 16 , wherein the current controller performs the first current-limiting operation in a manner that sets the current flowing through the memory cell to the first limit current value.

18. The method according to claim 16 , wherein the second current-limiting operation limits the current flowing through the memory cell to the second limit current value.

19. The method according to claim 16 , wherein the second limit current value is higher than the first limit current value.

20. The method according to claim 16 , wherein the current controller performs the second current-limiting operation in a manner that sets the current flowing through the memory cell to the second limit current value.

21. The method according to claim 16 , wherein the current controller is electrically connected to the writing circuit.

22. The method according to claim 16 , wherein the memory cell comprises the variable resistance element.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Mori Yotaro
• Kitagawa Makoto

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title