Nonvolatile memory device and method of controlling the same

Patent metadata

Field	Value
Publication number	US-2016019959-A1
Application number	US-201514635448-A
Country	US
Kind code	A1
Filing date	Mar 2, 2015
Priority date	Jul 16, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.

First claim

What is claimed is:

1 . A nonvolatile memory device comprising:
a memory cell comprising a variable resistance element connected between a couple of wirings; and a control circuit that applies a voltage between the couple of wirings connected to the memory cell, in data rewriting, the control circuit repeatedly performing a first voltage application step of applying a first write voltage between the couple of wirings connected to the memory cell and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings connected to the memory cell and comparing a cell current flowing through the memory cell with a first threshold current, the steps being repeatedly performed until a magnitude relation of the cell current and the first threshold current satisfies a first condition, and if the first condition is satisfied, the control circuit performing a second voltage application step of applying a second write voltage higher than the first write voltage between the couple of wirings connected to the memory cell.

2 . The nonvolatile memory device according to claim 1 , wherein
the control circuit performs, after the second voltage application step is performed, a second verify step of applying a second voltage lower than the second write voltage between the couple of wirings connected to the memory cell and comparing the cell current with a second threshold current, and if a magnitude relation of the current flowing through the memory cell and the second threshold current does not satisfy a second condition, the control circuit repeatedly performs the second voltage application step and the second verify step until the second condition is satisfied.

3 . The nonvolatile memory device according to claim 2 , wherein
the data rewriting is a set operation decreasing a resistance of the variable resistance element, the first condition is satisfied if the cell current exceeds the first threshold current, the second condition is satisfied if the cell current exceeds the second threshold current, and the second threshold current is larger than the first threshold current.

4 . The nonvolatile memory device according to claim 2 , wherein
the data rewriting is a reset operation increasing a resistance of the variable resistance element, the first condition is satisfied if the cell current falls below the first threshold current, the second condition is satisfied if the cell current falls below the second threshold current, and the second threshold current is smaller than the first threshold current.

5 . The nonvolatile memory device according to claim 1 , wherein
the control circuit repeatedly performs the first voltage application step and the first verify step with the amount of the first write voltage being gradually increased.

6 . The nonvolatile memory device according to claim 1 , wherein
a plurality of the first wiring lines are arranged in a first direction perpendicular to a substrate at a predetermined pitch, the first wiring lines extending in a second direction parallel to the substrate, and a plurality of the second wiring lines are arranged in the second direction at a predetermined pitch, the second wiring lines extending in the first direction.

7 . The nonvolatile memory device according to claim 1 , further comprising an ECC circuit detecting a bit error of data read from the memory cell, wherein
at least one of the control circuit and the ECC circuit counts an amount of the bit error detected by the ECC circuit, and in the data rewriting, the control circuit does not perform the second voltage application step if an amount of the bit error is equal to or smaller than a predetermined rate, and the control circuit performs the second voltage application step if the amount of the bit error is larger than the predetermined rate.

8 . A method of controlling a nonvolatile memory device, the nonvolatile memory device comprising:
a memory cell comprising a variable resistance element connected between a couple of wirings; and a control circuit that applies a voltage between the couple of wirings connected to the memory cell, the method comprising: performing repeatedly, a first voltage application step of applying a first write voltage between the couple of wirings connected to the memory cell and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings connected to the memory cell and comparing a cell current flowing through the memory cell with a first threshold current, until a magnitude relation of the cell current and the first threshold current satisfies a first condition; and performing, if the first condition is satisfied, a second voltage application step of applying a second write voltage higher than the first write voltage between the couple of wirings connected to the memory cell.

9 . The method of controlling the nonvolatile memory device according to claim 8 , wherein
after the second voltage application step is performed, a second verify step of applying a second voltage lower than the second write voltage between the couple of wirings connected to the memory cell and comparing the cell current with a second threshold current is performed, and if a magnitude relation of the current flowing through the memory cell and the second threshold current does not satisfy a second condition, the second voltage application step and the second verify step are repeatedly performed until the second condition is satisfied.

10 . The method of controlling the nonvolatile memory device according to claim 9 , wherein
the data rewriting is a set operation decreasing a resistance of the variable resistance element, the first condition is satisfied if the cell current exceeds the first threshold current, the second condition is satisfied if the cell current exceeds the second threshold current, and the second threshold current is larger than the first threshold current.

11 . The method of controlling the nonvolatile memory device according to claim 9 , wherein
the data rewriting is a reset operation increasing a resistance of the variable resistance element, the first condition is satisfied if the cell current falls below the first threshold current, the second condition is satisfied if the cell current falls below the second threshold current, and the second threshold current is smaller than the first threshold current.

12 . The method of controlling the nonvolatile memory device according to claim 8 , wherein
the control circuit repeatedly performs the first voltage application step and the first verify step with the amount of the first write voltage being gradually increased.

13 . The method of controlling the nonvolatile memory device according to claim 8 , the nonvolatile memory device further comprising an ECC circuit detecting a bit error of data read from the memory cell, wherein
at least one of the control circuit and the ECC circuit counts an amount of the bit error detected by the ECC circuit, and in the data rewriting, the second voltage application step is not performed if an amount of the bit error is equal to or smaller than a predetermined rate, and the second voltage application step is performed if the amount of the bit error is larger than the predetermined rate.

14 . A nonvolatile memory device comprising:
a memory cell comprising a variable resistance element connected between a couple of wirings; and a control circuit applying a voltage between the couple of wirings connected to the memory cell, in data rewriting, the control circuit

Assignees

• Toshiba Kk

Inventors

• Takagi Takeshi
• Yamato Masaki
• Ode Hiroyuki
• Yamaguchi Takeshi
• Tanaka Toshiharu

Classifications

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C2213/71

  Three dimensional array · CPC title