Memory device and method of manufacturing memory device

Patent metadata

Field	Value
Publication number	US-10186658-B2
Application number	US-201314650448-A
Country	US
Kind code	B2
Filing date	Nov 21, 2013
Priority date	Dec 26, 2012
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

Provided is a storage apparatus provided with a plurality of storage elements having storage layers comprising a plurality of layers and electrodes, one layer among the plurality of layers being extended in a first direction and being shared by the plurality of storage elements disposed in the first direction, the electrodes being extended in a second direction that differs from the first direction and being shared by the plurality of storage elements disposed in the second direction.

First claim

The invention claimed is:

1. A memory device comprising:
a layer of conductive material, strips of the layer extend linearly in parallel along a first direction;
electrodes that extend from a substrate linearly in parallel along a second direction, the second direction is perpendicular to the first direction;
variable resistance material, a first portion of the variable resistance material is between a first one of the strips and a first one of the electrodes and a second portion of the variable resistance material is between the first one of the strips and a second one of the electrodes; and
an interlayer insulating layer between the layer and the substrate, the substrate is perpendicular to the second direction,
wherein the substrate includes a semiconductor material, the substrate touches the electrodes, and
wherein the conductive material includes a chalcogen element {S, Se, Te}, oxygen, and at least one transition metal element.

2. The memory device according to claim 1 , wherein the substrate is a silicon substrate.

3. The memory device according to claim 1 , wherein a CMOS circuit is on the substrate.

4. The memory device according to claim 1 , wherein the interlayer insulating layer is between one of the electrodes and another of the electrodes.

5. The memory device according to claim 1 , wherein the layer is an ion source layer.

6. The memory device according to claim 1 , wherein the transition metal element is a material from Group 4 titanium group{Ti, Zr, Hf}.

7. The memory device according to claim 1 , wherein the transition metal element is a material from Group 5 vanadium group{V, Nb, Ta}.

8. The memory device according to claim 1 , wherein the transition metal element is a material from Group 6 chromium group{Cr, Mo, W}.

9. The memory device according to claim 1 , wherein the variable resistance material is configured of an oxide film, a nitride film, or an oxynitride film of a metal element.

10. The memory device according to claim 1 , wherein the variable resistance material is connected in series to a non-linear element.

11. The memory device according to claim 10 , wherein the non-linear element is configured of a pn junction diode, a metal/insulator/semiconductor diode, a metal/insulator/metal diode, a metal/semiconductor/metal diode, or a varistor.

12. The memory device according to claim 1 , wherein a first portion of the variable resistance material is between the first one of the strips and the first one of the electrodes.

13. The memory device according to claim 12 , wherein the layer is between the interlayer insulating layer and a different interlayer insulating layer, the interlayer insulating layer and the different interlayer insulating layer physically touch the first portion of the variable resistance material.

14. The memory device according to claim 12 , wherein the first one of the electrodes and the first one of the strips physically touch the first portion of the variable resistance material.

15. The memory device according to claim 12 , wherein a second portion of the variable resistance material is between the first one of the strips and a second one of the electrodes.

16. The memory device according to claim 15 , wherein the first one of the electrodes and the second one of the electrodes are of a same material.

17. The memory device according to claim 15 , wherein the first one of the strips and the second one of the electrodes physically touch the second portion of the variable resistance material.

18. The memory device according to claim 15 , wherein a third portion of the variable resistance material is between the second one of the electrodes and a third one of the strips.

19. The memory device according to claim 18 , wherein the second one of the electrodes and the third one of the strips physically touch the third portion of the variable resistance material.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Nonoguchi seiji
• Sone Takeyuki
• Ikarashi Minoru
• Narisawa Hiroaki
• Aratani Katsuhisa

Classifications

• G11C2213/71

  Three dimensional array · CPC title

• H01L27/2463

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L45/00

  Electricity · mapped topic

• H01L45/1683

  Electricity · mapped topic