Continuous carry-chain packing

Patent metadata

Field	Value
Publication number	US-11016733-B2
Application number	US-201816145151-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

The present disclosure relates generally to techniques for enhancing packing density of carry-chains implemented on an integrated circuit. In particular, a packed-carry chain may be implemented to redistribute and/or emulate the logic of a first number of arithmetic logic cells of a first and/or second carry-chain using a second number of arithmetic logic cells less than or equal to the first number. By fitting the first and second carry-chain into such a packed carry-chain, the area consumed to perform the arithmetic operations of the first and second carry-chain may be reduced. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., wiring, area, and power).

First claim

What is claimed is:

1. Packed carry-chain circuitry on an integrated circuit device, the packed carry-chain circuitry comprising:
first carry-chain circuitry, wherein the first carry-chain circuitry comprises a first number of logic cells each implemented to perform a respective first arithmetic operation; and
second carry-chain circuitry, wherein the second carry-chain circuitry comprises a second number of logic cells each implemented to perform a respective second arithmetic operation independently from the first arithmetic operations of the first carry-chain circuitry;
wherein the packed carry-chain circuitry is configured to perform the respective first arithmetic operation and the second arithmetic operation; and
wherein at least one logic cell of the first number of logic cells is used by the first number of logic cells to perform the respective first arithmetic operation and is included in the second number of logic cells, wherein the at least one logic cell is configured to physically couple the first carry-chain circuitry to the second carry-chain circuitry, and wherein the at least one logic cell is configured to maintain logical separation between the first carry-chain circuitry and the second carry-chain circuitry without a dummy arithmetic cell between the first carry-chain circuitry and the second carry-chain circuitry.

2. The packed carry-chain circuitry of claim 1 , wherein a first logic cell of the first number of logic cells comprises a set of look up tables (LUTs).

3. The packed carry-chain circuitry of claim 2 , wherein the set of LUTs is configured to determine a result of a combinatorial function based at least in part on an input received at the first logic cell.

4. The packed carry-chain circuitry of claim 3 , wherein the combinatorial function comprises one or more of an exclusive OR function or a logical AND function.

5. The packed carry-chain circuitry of claim 2 , wherein the first logic cell of the first number of logic cells comprises a multiplexor (mux) communicatively coupled to each of the set of LUTs.

6. The packed carry-chain circuitry of claim 1 , wherein the at least one logic cell comprises a most significant logic cell of the first carry-chain circuitry and wherein the at least one logic cell comprises a least significant logic cell of the second carry-chain circuitry.

7. The packed carry-chain circuitry of claim 6 , wherein the most significant logic cell of the first carry-chain comprises unused carry-out circuitry, and wherein the least significant logic cell of the second carry-chain comprises unused output circuitry.

8. The packed carry-chain circuitry of claim 1 , wherein the at least one logic cell comprises a pair of shared arithmetic logic cells, wherein the pair of shared arithmetic logic cells comprise two most significant logic cells of the first carry-chain circuitry and two least significant logic cells of the second carry-chain.

9. The packed carry-chain circuitry of claim 8 , wherein the two most significant logic cells of the first carry-chain circuitry comprise unused carry-out circuitry, and wherein the least significant logic cells of the second carry-chain comprise unused output circuitry.

10. The packed carry-chain circuitry of claim 8 , wherein a shared arithmetic logic cell of the pair of shared arithmetic logic cells comprises first carry-in circuitry and second carry-in circuitry.

11. The packed carry-chain circuitry of claim 10 , wherein the shared arithmetic logic cell comprises adder circuitry communicatively coupled to the first carry-in circuitry and second carry-in circuitry.

12. The packed carry-chain circuitry of claim 1 , wherein dot-product circuitry implemented on the integrated circuit device comprises the first carry-chain circuitry.

13. The packed carry-chain circuitry of claim 1 , wherein the integrated circuit device comprises a field-programmable gate array.

14. A method for generating packed carry-chain circuitry on an integrated circuit device, comprising:
identifying first carry-chain circuitry configurable to fit into the packed carry-chain circuitry, wherein the first carry-chain circuitry is configured to perform a first arithmetic operation, and wherein the first carry-chain circuitry comprises first arithmetic logic circuitry and a first number of logic cells each implemented to perform a respective first arithmetic operation;
identifying second carry-chain circuitry configurable to fit into the packed carry-chain circuitry, wherein the second carry-chain circuitry is configured to perform a second arithmetic operation, wherein the second arithmetic operation is independent from the first arithmetic operation, and wherein the second carry-chain comprises second arithmetic logic circuitry and a second number of logic cells each implemented to perform a respective second arithmetic operation; and
configuring at least one logic cell of the first number of logic cells used by the first number of logic cells to perform the respective first arithmetic operation to be included in the second number of logic cells, wherein the packed carry-chain circuitry is configured to perform the respective first arithmetic operation and the second arithmetic operation, wherein the at least one logic cell is configured to physically couple the first carry-chain circuitry to the second carry-chain circuitry, and wherein the at least one logic cell is configured to maintain logical separation between the first carry-chain circuitry and the second carry-chain without a dummy arithmetic cell between the first carry-chain circuitry and the second carry-chain circuitry.

15. The method of claim 14 , wherein the first arithmetic logic circuitry is configured to determine a result of a signed addition operation.

16. The method of claim 15 , wherein the first arithmetic logic circuitry comprises input circuitry, wherein the first arithmetic logic circuitry is configured to perform the first arithmetic operation based at least in part on a value received at the input circuitry, wherein the second arithmetic logic circuitry is configured to perform the second arithmetic operation independently from the value, and the method further comprising configuring the first carry-chain circuitry and the second carry-chain circuitry in the packed carry-chain circuitry by:
configuring the packed carry-chain circuitry to perform the first arithmetic operation independently from the value; and
configuring the packed carry-chain circuitry to perform the second arithmetic operation based at least in part on the value.

17. The method of claim 14 , comprising:
determining that the first arithmetic logic circuitry comprises unused carry-out circuitry; and
determining that the second arithmetic logic circuitry comprises unused output circuitry.

18. The method of claim 14 , wherein the packed carry-chain circuitry comprises a third number of arithmetic logic cells, and wherein the third number of arithmetic logic cells is less than a total number of logic cells included in the first number of logic cells and the second number of logic cells.

19. A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions to construct packed carry-chain circuitry on an integrated circuit device that, when executed by one or more processors, cause the processors to:
identify first carry-chain circuitry configurable to fit into the packed carry-chain circuitry, wherein the first carry-chain circuitry is configured to perform a first arithmetic operation, and wherein the first carry-chain co

Assignees

• Intel Corp

Inventors

• Langhammer Martin
• Gribok Sergey Vladimirovich
• Baeckler Gregg William

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F7/503

  using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal · CPC title

• G06F7/509

  for multiple operands, e.g. digital integrators · CPC title

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title