Techniques and devices for performing arithmetic

Patent metadata

Field	Value
Publication number	US-2016246571-A1
Application number	US-201415025770-A
Country	US
Kind code	A1
Filing date	Oct 2, 2014
Priority date	Oct 2, 2013
Publication date	Aug 25, 2016
Grant date	—

Abstract

A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.

First claim

1 . A device, comprising:
a producer circuit configured to:
receive one or more bits encoding a first addend,
receive a bit of a second addend,
produce, using at least one of the one or more bits encoding the first addend, a bit of the first addend,
provide, at a first output, a result equal to an exclusive-OR of the bit of the first addend and the bit of the second addend, and
provide, at a second output, the bit of the first addend or the bit of the second addend; and
an adder circuit having a first input coupled to the first output of the producer circuit, having a second input coupled to the second output of the producer circuit, having a third input coupled to receive a carry-in bit, and configured to provide a result equal to a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.

2 . The device of claim 1 , wherein the producer circuit includes:
a first programmable logic circuit (PLC) having an output configured to provide the bit of the first addend; a second programmable logic circuit (PLC) having an output configured to provide an inverse of the bit of the first addend; and a first selection circuit having a first data input coupled to the output of the first PLC, a second data input coupled to the output of the second PLC, a control input coupled to receive the bit of the second addend, and an output configured to provide the result equal to the exclusive-OR of the bit of the first addend and the bit of the second addend.

3 . The device of claim 2 , wherein the adder circuit includes:
a second selection circuit having a first data input coupled to the output of the first PLC, a second data input coupled to receive the carry-in bit, a control input coupled to the output of first selection circuit, and an output configured to provide a result equal to a carry-out bit of a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit; and a sum-bit circuit having a first input coupled to the output of the first selection circuit, a second input coupled to receive the carry-in bit, and an output configured to provide a result equal to a sum bit of the sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.

4 . The device of claim 1 , wherein the device is implemented on a field-programmable gate array (FPGA).

5 . A two-operand adder circuit, comprising:
a first programmable logic circuit (PLC) having an output configured to provide a bit of a first addend; a second programmable logic circuit (PLC) having an output configured to provide an inverse of the bit of the first addend; a first selection circuit having a first data input coupled to the output of the first PLC, a second data input coupled to the output of the second PLC, a control input coupled to receive a bit of a second addend, and an output configured to provide a result equal to an exclusive-OR of the bit of the first addend and the bit of the second addend; a second selection circuit having a first data input coupled to the output of the first PLC, a second data input coupled to receive a carry-in bit, a control input coupled to the output of first selection circuit, and an output configured to provide a result equal to a carry-out bit of a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit; and a sum-bit circuit having a first input coupled to the output of the first selection circuit, a second input coupled to receive the carry-in bit, and an output configured to provide a result equal to a sum bit of a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.

6 . The two-operand adder circuit of claim 5 , wherein inputs of the first PLC are coupled to respective inputs of the second PLC.

7 . The two-operand adder circuit of claim 5 , wherein:
the two-operand adder circuit comprises a third programmable logic circuit (PLC), the third PLC includes: the first PLC, the second PLC, and the first selection circuit, a first output of the third PLC is coupled to the output of the first selection circuit, a second output of the third PLC is coupled to the output of the first PLC, first inputs of the third PLC are coupled to respective inputs of the first PLC and to respective inputs of the second PLC, and a second input of the third PLC is coupled to the control input of the first selection circuit.

8 . The two-operand adder circuit of claim 6 , wherein the first PLC comprises a five-input lookup table (LUT), and wherein the second PLC comprises a five-input lookup table (LUT).

9 . The two-operand adder circuit of claim 7 , wherein the first PLC, the second PLC, and the first selection circuit are configured to operate as a six-input lookup table (LUT).

10 . The two-operand adder circuit of claim 5 , wherein the first selection circuit comprises a multiplexer.

11 . The two-operand adder circuit of claim 5 , wherein the second selection circuit comprises a multiplexer.

12 . The two-operand adder circuit of claim 5 , wherein the sum-bit circuit comprises an exclusive-OR gate.

13 . The two-operand adder circuit of claim 5 , further comprising a third selection circuit having a first data input coupled to the output of the first PLC, a second data input, a control input, and an output coupled to the first data input of the second selection circuit.

14 . The two-operand adder circuit of claim 13 , wherein the third selection circuit comprises a multiplexer.

15 . The two-operand adder circuit of claim 13 , wherein the second data input of the third selection circuit is coupled to receive the bit of the second addend.

16 . The two-operand adder circuit of claim 5 , wherein:
the first addend comprises a first partial product, and the second addend comprises a second partial product.

17 . The two-operand adder circuit of claim 16 , wherein:
the first partial product comprises a partial product of a radix-4 modified-Booth multiplication operation, and the second partial product comprises a partial product of a radix-4 modified-Booth multiplication operation.

18 . The two-operand adder circuit of claim 16 , further comprising a fourth programmable logic circuit (PLC) configured to provide the bit of the second addend at an output of the fourth PLC, wherein the control input of the first selection circuit is coupled to the output of the fourth PLC.

19 . The two-operand adder circuit of claim 6 , wherein the inputs of the first and second PLCs are coupled to receive one or more bits of a first operand of a multiplication operation and one or more bits of a second operand of a multiplication operation.

20 . A field-programmable gate array (FPGA) comprising the two-operand adder circuit of claim 5 .

21 - 22 . (canceled)

23 . A device, comprising:
a first and a second two-operand adder circuit, each comprising;
a first programmable logic circuit (PLC) having an output configured to provide a bit of a first addend;
a second programmable logic circuit (PLC) having an output configured to provide an inverse of the bit of the first addend;
a first selection circuit having a first data input coupled to the output of the first PLC, a second data input coupled to the output of the second PLC, a control input coupled to receive a bit of a second addend, and an output configured to provide a result equal to an exclusive-OR of the bit of the first addend and the bit of the second addend;
a second selection circuit h

Assignees

• Penn State Res Found

Inventors

• Walters Iii Eugene George

Classifications

• G06F7/501

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/5057 Primary

  using table look-up; using programmable logic arrays (G06F7/509 takes precedence) · CPC title

• G06F7/575

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title