Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction

Patent metadata

Field	Value
Publication number	US-11011633-B2
Application number	US-202016739093-A
Country	US
Kind code	B2
Filing date	Jan 9, 2020
Priority date	Jul 11, 2005
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

First claim

What is claimed is:

1. A method of operating a module, the module including at least one integrated circuit chip comprising a plurality of series N-type metal oxide semiconductor (NMOS) field effect transistors configured in a series connected stack configuration that comprises at least one series NMOS field effect transistor including a body, wherein the body of the at least one field effect transistor is electrically coupled to at least two accumulated charge sinks and wherein the at least two accumulated charge sinks are coupled through a path having low impedance, the at least one series NMOS field effect transistor either to pass an RF signal in a series enable state or to not pass the RF signal in a series disable state, the method further comprising:
electrically biasing the body of the at least one series NMOS field effect transistor of the module in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, a DC voltage level of a source of the at least one series NMOS field effect transistor of the module, and a DC voltage level of a drain of the at least one series NMOS field effect transistor of the module.

2. The method of claim 1 , wherein the electrically biasing the body of the at least one series NMOS field effect transistor in the series disable state comprises respectively electrically biasing a plurality of bodies of the plurality of series NMOS field effect transistors in the series disable state, wherein the bodies of the plurality of series NMOS field effect transistors are respectively electrically coupled to at least two accumulated charge sinks and wherein the at least two accumulated charge sinks are respectively coupled through a path having low impedance.

3. The method of claim 2 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors for a circuit operable in an RF switch on the at least one integrated circuit chip, which is implemented in silicon on insulator (SOI) technology.

4. The method of claim 3 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprising a substrate including a thin film silicon layer with a thickness less than 150 nm.

5. The method of claim 3 , wherein the respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors on the at least one integrated circuit chip, which is implemented in the SOI technology, comprising a thin film silicon layer on an insulating layer with sources and drains of respective NMOS field effect transistors of the plurality extending through the entire thickness of the thin film silicon layer to the insulating layer.

6. The method of claim 3 , wherein the electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistor in the series disable state comprises respectively electrically biasing the plurality of bodies of the plurality of series NMOS field effect transistors in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the sources of the plurality of series NMOS field effect transistors of the module, and the DC voltage level of the drains of the plurality of series NMOS field effect transistors of the module, comprises at least improving the linearity of the plurality of series NMOS field effect transistors.

7. The method of claim 2 , wherein the at least one integrated circuit chip comprises one or more additional pluralities of series N-type metal oxide semiconductor (NMOS) field effect transistors respectively in one or more additional series connected stack configurations;
and further comprising: respectively electrically biasing one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors in the series disable state, wherein the bodies of the one or more additional pluralities of series NMOS field effect transistors are respectively electrically coupled to at least two accumulated charge sinks and wherein the at least two accumulated charge sinks are respectively coupled through a path having low impedance, wherein the bodies of the one or more additional pluralities of series NMOS field effect transistors are respectively electrically biased to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the sources of the one or more additional pluralities of series NMOS field effect transistors of the module, and the DC voltage level of the drains of the one or more additional pluralities of series NMOS field effect transistors of the module.

8. The method of claim 7 , wherein the respectively electrically biasing the one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors comprises respectively electrically biasing the one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors for a circuit operable in an RF switch on the at least one integrated circuit chip, which is implemented in silicon on insulator (SOI) technology.

9. The method of claim 7 , wherein the respectively electrically biasing the one or more additional pluralities of bodies of the one or more additional pluralities of series NMOS field effect transistors comprises at least improving the linearity of the one or more additional pluralities of series NMOS field effect transistors.

10. A method of operating a communication device, the communication device including at least one integrated circuit chip comprising a plurality of series N-type metal oxide semiconductor (NMOS) field effect transistors configured in a series connected stack configuration that comprises at least one series NMOS field effect transistor including a body, wherein the body of the at least one field effect transistor is electrically coupled to at least two accumulated charge sinks and wherein the at least two accumulated charge sinks are coupled through a path having low impedance, the at least one series NMOS field effect transistor either to pass an RF signal in a series enable state or to not pass the RF signal in a series disable state, the method further comprising:
electrically biasing the body of the at least one series NMOS field effect transistor of the communication device in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, the DC voltage level of the source of the at least one series NMOS field effect transistor of the communication device, and the DC voltage level of the drain of the at least one series NMOS field effect transistor of the communication device.

11. The method of claim 10 , wherein the electrically biasing the body of the at least one series NMOS field effect transistor in the

Assignees

• Psemi Corp

Inventors

• Brindle Christopher N
• Deng Jie
• Genc Alper
• Yang Chieh-Kai

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/125

  Shapes of junctions between the regions · CPC title