Memory field-effect transistors and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11004868-B2
Application number	US-201716487417-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Mar 22, 2017
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.

First claim

What is claimed is:

1. An integrated device, comprising:
a substrate comprising a semiconductor material;
a gate conductor having a bottom surface facing the substrate and a lateral surface extending away from the substrate; and
a ferroelectric material separating the gate conductor from the substrate, a thickness of the ferroelectric material being greater along the bottom surface of the gate conductor than along the lateral surface of the gate conductor, wherein the ferroelectric material comprises a base layer and a conformal layer, the base layer along the bottom surface of the gate conductor without extending up the lateral surface of the gate conductor and the conformal layer substantially evenly covering the bottom surface of the gate conductor and the lateral surface of the gate conductor.

2. The integrated device of claim 1 , wherein the base layer is between a portion of the conformal layer and the gate conductor.

3. The integrated device of claim 1 , wherein a portion of the conformal layer is between the base layer and the gate conductor.

4. The integrated device of claim 1 , wherein the ferroelectric material comprises at least one of hafnium zirconium oxide, hafnium oxide, zirconium oxide, or a doped form of the hafnium zirconium oxide, the hafnium oxide, or the zirconium oxide.

5. The integrated device of claim 1 , wherein the gate conductor is a first gate conductor of a memory field-effect transistor and the ferroelectric material is a first gate insulator of the memory field-effect transistor, the integrated device further comprising:
a second gate conductor of a logic field-effect transistor over the substrate, the second gate conductor having a second bottom surface facing the substrate and second lateral surfaces extending away from the substrate; and
a second gate insulator of the logic field-effect transistor separating the second gate conductor from the substrate, a second thickness of the second gate insulator being substantially the same along the second bottom surface of the second gate conductor and along the second lateral surfaces of the second gate conductor.

6. The integrated device of claim 5 , wherein the thickness of the ferroelectric material along the bottom surface of the gate conductor is greater than the second thickness of the second gate insulator along the second bottom surface of the second gate conductor.

7. The integrated device of claim 5 , wherein the ferroelectric material comprises zirconium and oxygen and the second gate insulator is absent zirconium and comprises oxygen and one of hafnium or silicon.

8. The integrated device of claim 7 , wherein the ferroelectric material comprises a laminate of at least one layer of hafnium zirconium oxide and at least one layer of hafnium oxide.

9. The integrated device of claim 5 , wherein the gate conductor and the second gate conductor comprise the same material.

10. The integrated device of claim 9 , wherein the material comprises at least one of titanium, tantalum, tungsten, aluminum, vanadium, platinum, or lutetium.

11. A method to manufacture a field-effect transistor, comprising:
forming a sacrificial gate on a substrate comprising a semiconductor material;
removing the sacrificial gate to define a trench, the trench to define a shape of at least one of a gate insulator or a gate conductor, the gate insulator comprising a ferroelectric material;
forming the gate insulator of the field-effect transistor on the substrate and within the trench by forming a base layer of the ferroelectric material at a base of the trench without forming additional ferroelectric material up walls of the trench and by forming a conformal layer of the ferroelectric material using conformal deposition of the ferroelectric material, the conformal layer covering both the base of the trench and walls of the trench substantially evenly; and
forming the gate conductor on the gate insulator, a first thickness of the gate insulator along a bottom surface of the gate conductor being greater than a second thickness of the gate insulator along each lateral surface of the gate conductor.

12. The method of claim 11 , wherein the base layer is formed on the substrate before forming the sacrificial gate, the sacrificial gate being formed on the base layer.

13. The method of claim 11 , wherein the base layer is formed at the base of the trench after formation of the conformal layer, the base layer being formed on top of the conformal layer.

14. The method of claim 11 , wherein the base layer is formed at the base of the trench before formation of the conformal layer, the conformal layer being formed on top of the base layer.

15. The method of claim 11 , wherein the field-effect transistor is a memory field-effect transistor.

16. The method of claim 15 , further comprising:
forming a first sacrificial gate on the substrate to define a first space in which the gate conductor of the memory field-effect transistor is to subsequently be formed; and
forming a second sacrificial gate on the substrate to define a second space in which a gate metal of a logic field-effect transistor is to subsequently be formed, the first and second sacrificial gates being formed during a same manufacturing process.

17. The method of claim 16 , further comprising:
removing at least one of the first sacrificial gate or the second sacrificial gate, wherein structures of the memory field-effect transistor and the logic field-effect transistor prior to the removal of the at least one of the first sacrificial gate or the second sacrificial gate are substantially identical being formed as a result of the same processes.

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Avci Uygar E
• Howard Joshua M
• Young Ian A
• Morris Daniel H

Classifications

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L29/516

  Electricity · mapped topic

• H01L27/1159 Primary

  Electricity · mapped topic