Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11004773-B2
Application number	US-201916391632-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Apr 23, 2019
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.

First claim

What is claimed is:

1. A semiconductor structure comprising a first semiconductor die, wherein the first semiconductor die comprises:
a first semiconductor substrate having a front-side surface and a backside surface;

first semiconductor devices located on the front-side surface of the first semiconductor substrate;
a first dielectric material layer located on the first semiconductor devices and having formed therein conductive via structures contacting nodes of the first semiconductor devices;
a second dielectric material layer located on the first dielectric material layer, wherein the second dielectric material layer is more distal from the first semiconductor substrate than the first dielectric material layer is from the first semiconductor substrate;
a metal interconnect structure that is not in direct contact with the first semiconductor substrate located in the second dielectric material layer; and
a through-substrate via structure extending from a backside surface of the first semiconductor substrate to a proximal surface of the metal interconnect structure, wherein a horizontal portion of the through-substrate via structure that contacts the proximal surface of the metal interconnect structure comprises a porous metallic material portion having a porosity in a range from 20% to 80%.

2. The semiconductor structure of claim 1 , further comprising a porous dielectric material layer located between the first dielectric material layer and the second dielectric material layer and laterally surrounding the horizontal portion of the through-substrate via structure.

3. The semiconductor structure of claim 2 , wherein the porous dielectric material layer has a porosity in a range from 20% to 80%.

4. The semiconductor structure of claim 2 , wherein the porous dielectric material layer comprises a continuous network of pores that extends from a proximal horizontal surface of the porous dielectric material layer to a distal horizontal surface of the porous dielectric material layer.

5. The semiconductor structure of claim 4 , wherein the porous metallic material portion is formed within the continuous network of pores within the porous dielectric material layer.

6. The semiconductor structure of claim 2 , further comprising a solid metallic material portion that comprises a same metallic material as the porous metallic material portion and is adjoined to the porous metallic material portion.

7. The semiconductor structure of claim 6 , wherein the porous metallic material portion comprises a continuous network of percolating metallic particles formed within a continuous porous dielectric matrix, wherein a combination of the continuous network of percolating metallic particles and the continuous porous dielectric matrix complementarily fill at least 95% of a volume between the solid metallic material portion and the metal interconnect structure.

8. The semiconductor structure of claim 6 , wherein the same metallic material comprises at least one material selected from TiN, TaN, and WN.

9. The semiconductor structure of claim 2 , wherein the porous dielectric material layer comprises a porous organosilicate glass and has a thickness in a range from 6 nm to 60 nm.

10. The semiconductor structure of claim 2 , further comprising:
a via opening extending through the first semiconductor substrate and the first dielectric material layer with a straight sidewall; and
a tubular dielectric spacer located on the straight sidewall of the via opening, wherein the through-substrate via structure extends through, and contacts an inner sidewall of, the tubular dielectric spacer.

11. The semiconductor structure of claim 10 , wherein an annular end surface of the tubular dielectric spacer is vertically spaced from the metal interconnect structure at least by a thickness of the porous dielectric material layer.

12. The semiconductor structure of claim 1 , further comprising:
an external bonding pad contacting the through-substrate via structure and located over the backside surface of the first semiconductor substrate;
a solder ball bonded to the external bonding pad; and
a bonding wire attached to the solder ball.

13. The semiconductor structure of claim 1 , further comprising a second semiconductor die bonded to the first semiconductor die via die-to-die bonding, wherein the front-side surface of the first semiconductor substrate is more proximal to the second semiconductor die than the backside surface is to the second semiconductor die.

14. The semiconductor structure of claim 13 , wherein:
the second semiconductor die comprises a memory die comprising a three-dimensional array of memory elements therein; and
the first semiconductor devices in the first semiconductor die comprises a peripheral circuitry configured to control operation of the three-dimensional array of memory elements.

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Chen
• Rabkin Peter
• Higashitani Masaaki

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/665

  Porous materials · CPC title