Semiconductor devices having through-electrodes and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9847276-B2
Application number	US-201414463645-A
Country	US
Kind code	B2
Filing date	Aug 19, 2014
Priority date	Nov 20, 2013
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a top surface and a bottom surface disposed on an opposite side of the semiconductor substrate from the top surface;
an interlayer dielectric layer provided on the top surface of the semiconductor substrate, the interlayer dielectric layer including an integrated circuit;
an inter-metal dielectric layer provided on the interlayer dielectric layer, the inter-metal dielectric layer including at least one metal interconnection electrically connected to the integrated circuit, the inter-metal dielectric layer including a plurality of low-k dielectric layers and a plurality of insulating capping layers, each of the plurality of low-k dielectric layers and each of the plurality of insulating capping layers being alternately stacked on the interlayer dielectric layer in a first direction perpendicular to the top surface of the semiconductor substrate;
an upper dielectric layer disposed on the inter-metal dielectric layer;
a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate;
a via-dielectric layer surrounding an outer surface of the through-electrode, the via-dielectric layer electrically insulating the through-electrode from the semiconductor substrate,
wherein the via-dielectric layer includes a body and a plurality of protrusions,
wherein the body of the via-dielectric layer is extended in the first direction along a sidewall of the through-electrode,
wherein each of the plurality of protrusions is extended in a second direction crossing the first direction from the body toward one of the plurality of the low-k dielectric layers,
wherein each of the plurality of protrusions is simultaneously in contact with a sidewall of each of the plurality of the low-k dielectric layers and a bottom surface of each of the plurality of the insulating capping layers, and
wherein each of the plurality of protrusions and each of the plurality of insulating capping layers are alternately stacked in the first direction on the top surface of the semiconductor substrate; and
a barrier layer between the through-electrode and the via-dielectric layer.

2. The semiconductor device of claim 1 ,
wherein the through-electrode fills a via-hole penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, and
wherein the body of the via-dielectric layer extends along an inner sidewall of the via-hole.

3. The semiconductor device of claim 2 , further comprising:
a plurality of air-gaps, each of the plurality of air-gaps being surrounded by one of the plurality of protrusions,
wherein each of the plurality of protrusions inserted into a space between two adjacent insulating capping layers of the plurality of insulating capping layers.

4. The semiconductor device of claim 3 ,
wherein the plurality of low-k dielectric layers has a dielectric constant lower than that of silicon dioxide, and
wherein the protrusions protrude toward the low-k dielectric layers in the second direction.

5. The semiconductor device of claim 4 ,
wherein the air-gaps are spaced apart from each other with the insulating capping layers therebetween in the first direction.

6. The semiconductor device of claim 1 , further comprising:
an upper interconnection disposed on the upper dielectric layer,
wherein the through-electrode further penetrates the upper dielectric layer and is connected to the upper interconnection.

7. The semiconductor device of claim 1 , further comprising:
an upper terminal disposed on the upper dielectric layer,
wherein the upper terminal penetrates the upper dielectric layer and is connected to the metal interconnection electrically connected to the through-electrode.

8. The semiconductor device of claim 1 , further comprising:
a plurality of air-gaps, each of the plurality of air-gaps being surrounded by one of the plurality of protrusions,
wherein the plurality of low-k dielectric layers has a dielectric constant lower than that of silicon dioxide, and
wherein the low-k dielectric layers include recess regions extending from the via-dielectric layer in the second direction.

9. The semiconductor device of claim 8 ,
wherein the recess regions are partially filled with the via-dielectric layer, and
wherein the plurality of air-gaps is defined by spaces incompletely filled with the via-dielectric layer in the recess regions.

10. The semiconductor device of claim 8 ,
wherein the recess regions are spaced apart from each other with the insulating capping layers therebetween in the first direction.

11. A semiconductor device comprising:
a semiconductor substrate having a top surface and a bottom surface disposed on an opposite side of the semiconductor substrate from the top surface;
an interlayer dielectric layer provided on the top surface of the semiconductor substrate, the interlayer dielectric layer including an integrated circuit;
an inter-metal dielectric layer provided on the interlayer dielectric layer, the inter-metal dielectric layer including at least one metal interconnection electrically connected to the integrated circuit;
a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate;
a via-dielectric layer surrounding the through-electrode, the via-dielectric layer electrically insulating the through-electrode from the semiconductor substrate; and
a barrier layer between the through-electrode and the via-dielectric layer,
wherein the via-dielectric layer includes a porous dielectric layer including one or more voids between the inter-metal dielectric layer and the through-electrode,
wherein the inter-metal dielectric layer includes:
a plurality of low-k dielectric layers stacked on the interlayer dielectric layer in a first direction perpendicular to the top surface of the semiconductor substrate; and
a plurality of insulating capping layers provided between the plurality of low-k dielectric layers,

wherein the voids are disposed in the via-dielectric layer and disposed between two adjacent insulating capping layers among the plurality of insulating capping layers,
wherein the voids and the plurality of insulating capping layers are overlapped in the first direction, and
wherein the via-dielectric layer is simultaneously in contact with a sidewall of each of the plurality of the low-k dielectric layers and a bottom surface of each of the plurality of the insulating capping layers.

12. The semiconductor device of claim 11 ,
wherein the plurality of low-k dielectric layers has a dielectric constant lower than that of silicon dioxide.

13. The semiconductor device of claim 1 ,
wherein the via-dielectric layer is extended to be in contact with a top surface of the upper dielectric layer.

14. The semiconductor device of claim 11 , further comprising:
an upper dielectric layer disposed on the inter-metal dielectric layer,
wherein the via-dielectric layer is extended to be in contact with a top surface of the upper dielectric layer.

Assignees

• Kang Pil-Kyu
• Park Byung Lyul
• Kang Sunghee
• Kim Taeseong
• Kim Taeyeong
• Moon Kwangjin
• Park Jae-Hwa
• Bang Sukchul
• Son Seongmin
• An Jin Ho
• Lee Ho-Jin
• Jin Jeonggi
• Samsung Electronics Co Ltd

Inventors

• Kang Pil-Kyu
• Park Byung Lyul
• Kang Sunghee
• Kim Taeseong
• Kim Taeyeong
• Moon Kwangjin
• Park Jae-Hwa
• Bang Sukchul
• Son Seongmin
• An Jin Ho
• Lee Ho-Jin
• Jin Jeonggi

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title