Superconducting device with multiple thermal sinks

Patent metadata

Field	Value
Publication number	US-11004763-B2
Application number	US-201816227965-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Dec 20, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first thermal sink layer;
a first ground plane associated with a first set of circuits that have a first operational temperature requirement, wherein the first ground plane and the first set of circuits are formed of a first electrically conducting material, and the first ground plane and the first set of circuits reside in a first dielectric layer overlying a substrate;
a first thermally conductive via that couples the first ground plane to the first thermal sink layer;
a second thermal sink layer;
a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, wherein the second ground plane and the second set of circuits are formed of a second electrically conducting material that has a different operating temperature requirement than the first electrically conducting material, and the second ground plane and the second set of circuits reside in a second dielectric layer overlying the substrate and one of overlying and underlying the first dielectric layer, wherein the first dielectric layer has a thickness that prevents coupling between phonons in the first ground plane and phonons in the second ground plane; and
a second thermally conductive via that couples the second ground plane to the second thermal sink layer, wherein the first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement, wherein the first and second thermal sink layers are not formed of a superconductive material.

2. The circuit of claim 1 , wherein the first thermal sink layer, the second thermal sink layer, the first thermally conductive via and the second thermally conductive via are formed of copper.

3. The circuit of claim 1 , wherein the first ground plane is formed from Aluminum, and the second ground plane is formed of Niobium.

4. The circuit of claim 1 , wherein the first thermally conductive via is one of a plurality of first thermally conductive vias that each couple the first ground plane to the first thermal sink layer, and the second thermally conductive via is one of a plurality of second thermally conductive vias that each couple the second ground plane to the second thermal sink layer.

5. A monolithic microwave integrated circuit (MMIC) comprising:
a first electrically conducting ground plane associated with a first set of superconducting circuits that have a first operational temperature requirement, wherein the first electrically conducting ground plane and the first set of superconducting circuits are formed of a first electrically conducting material, and the first electrically conducting ground plane and the first set of superconducting circuits reside in a first dielectric layer overlying a substrate;
a second electrically conducting ground plane associated with a second set of superconducting circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, wherein the second electrically conducting ground plane and the second set of superconducting circuits are formed of a second electrically conducting material that has a different operating temperature requirement than the first electrically conducting material, and the second electrically conducting ground plane and the second set of superconducting circuits reside in a second dielectric layer overlying the substrate and one of overlying and underlying the first dielectric layer; wherein the first dielectric layer has a thickness that prevents coupling between phonons in the first electrically conducting ground plane and phonons in the second electrically conducting ground plane;
a first thermal sink layer disposed one of above or below the first and second electrically conducting ground planes;
a second thermal sink layer disposed the other of above or below the first and second electrically conducting ground planes, wherein the first and second thermal sink layers are not formed of a superconductive material;
a first set of thermally conductive vias that each couple the first electrically conducting ground plane to the first thermal sink layer; and
a second set of thermally conductive vias that each couple the second ground plane to the second thermal sink layer.

6. The circuit of claim 5 , wherein the first thermal sink layer, the second thermal sink layer, the first set of thermally conductive vias and the second set of thermally conductive vias are formed of copper.

7. The circuit of claim 5 , wherein the first electrically conducting ground plane is formed from Aluminum, and the second electrically conducting ground plane is formed of Niobium.

8. An integrated circuit comprising:
a plurality of thermal sink layers with each thermal sink layer being thermally isolated from each other thermal sink layer, wherein each thermal sink layer of the plurality of thermal sink layers is not formed of a superconductive material; and
a plurality of ground planes each being associated with a respective set of circuits that each have a different operational temperature requirement than the other, each of the plurality of ground planes being coupled to a respective thermal sink layer by a respective thermal via, wherein each thermal sink layer is cooled at a respective temperature to maintain its coupled ground plane at its respective operational temperature requirement,
wherein a first ground plane of the plurality of ground planes and a first set of circuits of the respective set of circuits associated with the first ground plane reside in a first dielectric layer overlying a substrate, and the first ground plane and the first set of circuits are formed of a first electrically conducting material,
wherein a second ground plane of the plurality of ground planes and a second set of circuits of the respective set of circuits associated with the second ground plane reside in a second dielectric layer overlying the substrate and one of overlying and underlying the first dielectric layer, wherein the second ground plane and the second set of circuits are formed of a second electrically conducting material that has a different operating temperature requirement than the first electrically conducting material, and
wherein the first dielectric layer has a thickness that prevents coupling between phonons in the first ground plane and phonons in the second ground plane.

9. The circuit of claim 8 , wherein each thermal sink layer, and each thermal via are formed of copper.

10. The circuit of claim 8 , wherein the first ground plane is formed from Aluminum, and the second ground plane is formed of Niobium.

11. The circuit of claim 8 , wherein each of the plurality of ground planes are coupled to a respective thermal sink layer by a plurality of respective thermal vias.

Assignees

• Hathaway Aaron Ashley
• Boyd Gregory R
• Przybysz John X
• Northrop Grumman Systems Corp

Inventors

• Hathaway Aaron Ashley
• Boyd Gregory R
• Przybysz John X

Classifications

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/203

  Electrical connections · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/4484

  Superconducting materials · CPC title

• H10W20/427

  Power or ground buses · CPC title