Semiconductor device and structure

Patent metadata

Field	Value
Publication number	US-9871034-B1
Application number	US-201213731108-A
Country	US
Kind code	B1
Filing date	Dec 30, 2012
Priority date	Dec 29, 2012
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; and a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, and the second layer overlying the at least one metal layer; wherein the material composition of at least one of the plurality of second single crystal transistors is substantially different than the material composition of at least one of the plurality of first transistors.

First claim

We claim:

1. An Integrated Circuit device, comprising:
a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;
at least one metal layer providing interconnection between said plurality of first transistors; and
a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;
a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; and
a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors;
wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid.

2. The Integrated Circuit device according to claim 1 , comprising at least one conductive layer underneath said second single crystal transistors,
wherein said at least one conductive layer comprises a plurality of strips controlled by at least one of said plurality of second single crystal transistors.

3. The Integrated Circuit device according to claim 1 ,
wherein said second layer comprises at least one buffer used to buffer a signal in-between at least two of said plurality of first transistors.

4. The Integrated Circuit device according to claim 1 , comprising at least one thermal conducting path from at least one of said plurality of second single crystal transistors to a heat sink,
wherein said thermal conducting path comprises a thermal conductivity greater than 10 W/m-K.

5. The Integrated Circuit device according to claim 1 , wherein said plurality of second single crystal transistors is aligned to said plurality of first transistors with less than 100 nm alignment error.

6. The Integrated Circuit device according to claim 1 , wherein said second layer comprises at least one conductive pad for connecting power from outside of said device to said second conductive grid.

7. The Integrated Circuit device according to claim 1 ,
wherein said second transistors comprise self-aligned LDD.

8. An Integrated Circuit device, comprising:
a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;
at least one metal layer providing interconnection between said plurality of first transistors;
a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;
a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; and
a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors;
wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid, and
wherein said second layer comprises a wireless structure providing wireless communication between said device and external devices.

9. The Integrated Circuit device according to claim 8 , comprising at least one conductive layer underneath said second single crystal transistors,
wherein said at least one conductive layer comprises a plurality of strips controlled by at least one of said plurality of second single crystal transistors.

10. The Integrated Circuit device according to claim 8 , wherein said wireless structure is aligned to said plurality of first transistors with less than 100 nm alignment error.

11. The Integrated Circuit device according to claim 8 ,
wherein said second transistors comprise self-aligned LDD.

12. The Integrated Circuit device according to claim 8 ,
wherein at least one of said plurality of second single crystal transistors comprises a second material composition and at least one of said plurality of first transistors comprises a first material composition, and
wherein said second material composition is substantially different than said first material composition.

13. The Integrated Circuit device according to claim 8 ,
wherein said second layer comprises at least one conductive pad for connecting power to said device.

14. The Integrated Circuit device according to claim 8 , further comprising:
a high quality oxide, said high quality oxide adapted for isolating at least two of said second transistors,
wherein said high quality oxide isolation has a leakage current of less than one picoamp per micron at device power supply and 25 degrees C.

15. An Integrated Circuit device, comprising:
a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;
at least one metal layer providing interconnection between said plurality of first transistors;
a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;
wherein said second layer comprises SerDes circuits, and

a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors;
a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors,
wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid; and

a connection path between at least one of said second transistors and at least one of said first transistors,
wherein said connection path comprises a through said second layer via with a diameter of 150 nm or less.

16. The Integrated Circuit device according to claim 15 , comprising at least one conductive layer underneath said second single crystal transistors, said at least one conductive layer comprises a plurality of strips controlled by at least one of said plurality of second single crystal transistors.

17. The Integrated Circuit device according to claim 15 , further comprising:
a high quality oxide, said high quality oxide adapted for isolating at least two of said second transistors,
wherein said high quality oxide isolation has a leakage current of less than one picoamp per micron at device power supply and 25 degrees C.

18. The Integrated Circuit device according to claim 15 , comprising at least one thermal conducting path from at least one of said plurality of second single crystal transistors to a heat sink,
wherein said thermal conducting path comprises a thermal conductivity greater than 10 W/m-K.

19. The Integrated Circuit device according to claim 15 ,
wherein at least one of said plurality of second single crystal transistors comprises a second material composition and at least one of said plurality of first transistors comprises a first material composition, and
wherein said second material composition is substantially different than said first material composition.

20. The Integrated Circuit device according to claim 15 ,
wherein said second transistors comprise self-aligned LDD.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi
• Cronquist Brian

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title