Display device for performing internal compensation of a pixel

Patent metadata

Field	Value
Publication number	US-10997910-B2
Application number	US-201816053580-A
Country	US
Kind code	B2
Filing date	Aug 2, 2018
Priority date	Nov 14, 2017
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A display device includes: a display panel including a first pixel, a second pixel adjacent to one side of the first pixel, and a third pixel adjacent to the other side of the first pixel; a first scan driver supplying a first signal to the first to third pixels through a first scan line; a second scan driver supplying a second scan signal to the second and third pixels through a second scan line when a first time elapses after the supply of the first scan signal is started; a data driver supplying a data voltage to a plurality of output lines; and a data divider selectively supplying the data voltage to data lines respectively coupled to the first to third pixels. Each of the second and third pixels includes a switching transistor controlled by the second scan signal.

First claim

What is claimed is:

1. A display device comprising:
a display panel including a first pixel, a second pixel adjacent to one side of the first pixel in a first direction, and a third pixel adjacent to the other side of the first pixel in the first direction, wherein each of the first pixel, the second pixel and the third pixel includes a first switching transistor electrically connected to a data line, wherein each of the second pixel and the third pixel further includes a second switching transistor which is serially connected to the first switching transistor of each of the second pixel and the third pixel, and wherein the second switching transistor is not connected to the first pixel;
a first scan driver connected to a gate electrode of the first switching transistor of each of the first pixel, the second pixel and the third pixel and configured to supply a first scan signal to the first pixel, the second pixel and the third pixel through a first scan line;
a second scan driver connected to a gate electrode of the second switching transistor of each of the second pixel and the third pixel, and configured to supply a second scan signal to the second pixel and the third pixel through a second scan line when a first time elapses after the supply of the first scan signal is started;
a data driver configured to supply data voltages to a plurality of output lines; and
a data divider configured to selectively supply the data voltages to data lines respectively coupled to the first to third pixels.

2. The display device of claim 1 , wherein the first scan signal has a first width, and the second scan signal has a second width smaller than the first width.

3. The display device of claim 2 , wherein gate-on periods of the first scan signal and the second scan signal are substantially simultaneously ended.

4. The display device of claim 1 , wherein the data divider selectively supplies the data voltages to the data lines in response to a first selection signal for selecting a data line coupled to the first pixel and a second selection signal for selecting a data line coupled to at least one of the second pixel and the third pixel.

5. The display device of claim 4 , wherein at least a portion of an enabling period of the first scan signal overlaps with at least a portion of an enabling period of the first selection signal and at least a portion of an enabling period of the second selection signal.

6. The display device of claim 5 , wherein at least a portion of an enabling period of the second scan signal overlaps with the at least a portion of an enabling period of the second selection signal.

7. The display device of claim 1 , wherein the first pixel emits green light, and each of the second pixel and the third pixel emits one of red light and blue light.

8. The display device of claim 1 , wherein each of the first to third pixels further comprises:
a first transistor coupled between a first node electrically coupled to a first power source and a second node electrically coupled to an anode electrode of an organic light emitting diode, the first transistor generating a driving current;
a second transistor coupled between the second node and a third node coupled to a gate electrode of the first transistor, the second transistor receiving the first scan signal through a gate electrode thereof;
a storage capacitor coupled between the first power source and the third node; and
the organic light emitting diode coupled between the second node and a second power source.

9. The display device of claim 8 , wherein the second switching transistor is coupled between one of the data lines and the first switching transistor, and receives the second scan signal through the gate electrode thereof.

10. The display device of claim 9 , wherein each of the first to third pixels further includes:
a fourth transistor coupled between the third node and an initialization power source, the fourth transistor receiving an initialization signal through a gate electrode thereof;
a fifth transistor coupled between the first power source and the first node, the fifth transistor receiving an emission control signal through a gate electrode thereof;
a sixth transistor coupled between the second node and the anode electrode of the organic light emitting diode, the sixth transistor receiving the emission control signal through a gate electrode thereof; and
a seventh transistor coupled between the initialization power source and the anode electrode of the organic light emitting diode, the seventh transistor receiving the first scan signal through a gate electrode thereof.

11. The display device of claim 10 , wherein the first pixel emits green light, and each of the second pixel and the third pixel emits one of red light and blue light.

12. The display device of claim 9 , wherein a turned-on time of the second switching transistor is shorter than that of the second transistor.

13. The display device of claim 12 , wherein the first switching transistor and the second transistor are substantially simultaneously turned off.

Assignees

• Samsung Display Co Ltd

Inventors

• Hwang Young In
• Gil Elly
• Lee Jin A
• Jo Joo Hyeon
• Chu Seong Baik

Classifications

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3659

  the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title