Gate driver for display device and display device including the same

Patent metadata

Field	Value
Publication number	US-2016240144-A1
Application number	US-201514836796-A
Country	US
Kind code	A1
Filing date	Aug 26, 2015
Priority date	Feb 12, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A gate driver for a display device and a display device including the same are disclosed. In one aspect, the gate driver includes first through N-th scan drivers configured to respectively output first through N-th scan signals, where N is an integer greater than 1. The gate driver also includes first through N-th sensing drivers configured to respectively output first through N-th sensing signals, wherein an M-th one of the first through N-th sensing drivers is configured to activate an M-th one of the first through N-th sensing signals K times during an active period of an (M+1)-th one of the first through N-th scan signals, where M is an integer greater than 0 and less than N and K is an integer greater than 1.

First claim

What is claimed is:

1 . A gate driver for a display device, the gate driver comprising:
first through N-th scan drivers configured to respectively output first through N-th scan signals, where N is an integer greater than 1; and first through N-th sensing drivers configured to respectively output first through N-th sensing signals, wherein an M-th one of the first through N-th sensing drivers is configured to activate an M-th one of the first through N-th sensing signals K times during an active period of an (M+1)-th one of the first through N-th scan signals, where M is an integer greater than 0 and less than N and K is an integer greater than 1.

2 . The gate driver of claim 1 , wherein the gate driver is embedded in a display panel of the display device.

3 . The gate driver of claim 1 , wherein the M-th sensing driver comprises:
a first transistor configured to output a sensing clock signal as the M-th sensing signal during an active period of an (M+1)-th carry signal based on the (M+1)-th carry signal output from an (M+1)-th one of the first through N-th scan drivers; and a second transistor configured to output a power supply voltage as the M-th sensing signal during an active period of an (M+2)-th carry signal based on the (M+2)-th carry signal output from an (M+2)-th one of the first through N-th scan drivers.

4 . The gate driver of claim 3 , wherein the sensing clock signal includes a plurality of pulses within the active period of the (M+1)-th carry signal.

5 . The gate driver of claim 3 , wherein the sensing clock signal includes a clock-active period and a clock-inactive period during the active period of the (M+1)-th carry signal, and
wherein the sensing clock signal includes a plurality of pulses within the clock-active period.

6 . The gate driver of claim 3 , wherein the first transistor is a first PMOS transistor including a first terminal configured to receive the sensing clock signal, a second terminal electrically connected to an output node of the M-th sensing driver, and a first gate terminal configured to receive the (M+1)-th carry signal, and
wherein the second transistor is a second PMOS transistor including a third terminal electrically connected to the output node of the M-th sensing driver, a fourth terminal configured to receive the power supply voltage, and a second gate terminal configured to receive the (M+2)-th carry signal.

7 . The gate driver of claim 1 , wherein the M-th sensing driver comprises:
a first transistor configured to output a sensing clock signal as the M-th sensing signal during an active period of an (M+1)-th carry signal based on the (M+1)-th carry signal output from an (M+1)-th one of the first through N-th scan drivers; and a second transistor configured to output a power supply voltage as the M-th sensing signal during an inactive period of the (M+1)-th carry signal based on the (M+1)-th carry signal.

8 . The gate driver of claim 7 , wherein the first transistor is a PMOS transistor including a first terminal configured to receive the sensing clock signal, a second terminal electrically connected to an output node of the M-th sensing driver, and a first gate terminal configured to receive the (M+1)-th carry signal, and
wherein the second transistor is an NMOS transistor including a third terminal electrically connected to the output node of the M-th sensing driver, a fourth terminal configured to receive the power supply voltage, and a second gate terminal configured to receive the (M+1)-th carry signal.

9 . The gate driver of claim 1 , wherein the M-th sensing driver comprises:
a first transistor configured to output a sensing clock signal as the M-th sensing signal during an active period of an (M+1)-th carry signal based on the (M+1)-th carry signal output from an (M+1)-th one of the first through N-th scan drivers; an inverter configured invert the (M+1)-th carry signal so as to generate an inverted (M+1)-th carry signal; and a second transistor configured to output a power supply voltage as the M-th sensing signal during an inactive period of the (M+1)-th carry signal based on the inverted (M+1)-th carry signal.

10 . The gate driver of claim 9 , wherein the first transistor is a first PMOS transistor including a first terminal configured to receive the sensing clock signal, a second terminal electrically connected to an output node of the M-th sensing driver, and a first gate terminal configured to receive the (M+1)-th carry signal, and
wherein the second transistor is a second PMOS transistor including a third terminal electrically connected to the output node of the M-th sensing driver, a fourth terminal configured to receive the power supply voltage, and a second gate terminal configured to receive the inverted (M+1)-th carry signal.

11 . The gate driver of claim 1 , wherein the first through N-th scan drivers and the first through N-th sensing drivers are formed in a peripheral region of a display panel included in the display device.

12 . The gate driver of claim 11 , wherein the first through N-th scan drivers and the first through N-th sensing drivers are alternately formed.

13 . The gate driver of claim 1 , wherein the first through N-th scan drivers are formed in a first peripheral region located on a first side of a display region of a display panel included in the display device, and
wherein the first through N-th sensing drivers are formed in a second peripheral region located on a second side opposite to the first side in the display region.

14 . The gate driver of claim 1 , wherein the first through N-th sensing drivers are further configured to output the first through N-th sensing signals in a sensing mode.

15 . A display device, comprising:
a display panel including a plurality of pixels; a source driver configured to provide a plurality of data signals to the pixels; and a gate driver configured to provide first through N-th scan signals and first through N-th sensing signals to the pixels, where N is an integer greater than 1, wherein the gate driver includes:
first through N-th scan drivers configured to respectively output the first through N-th scan signals through first through N-th scan lines; and
first through N-th sensing drivers configured to respectively output the first through N-th sensing signals through first through N-th sensing lines,
wherein an M-th one of the first through N-th sensing drivers is further configured to activate an M-th one of the first through N-th sensing signals K times during an active period of an (M+1)-th one of the first through N-th scan signals, where M is an integer greater than 0 and less than N and K is an integer greater than 1.

16 . The display device of claim 15 , wherein the gate driver is embedded in the display panel.

17 . The display device of claim 15 , wherein the source driver is further configured to provide one of the data signals to the pixels as a voltage applied via a data line, wherein a selected one of the pixels electrically connected to an M-th one of the first through N-th scan lines and an M-th one of the first through N-th sensing lines includes:
a switching transistor configured to transfer the applied voltage based on an M-th one of the first through N-th scan signals; a storage capacitor configured to store the transferred voltage; a driving transistor configured to generate a driving current based on the stored voltage; an organic light-emitting diode (OLED) configured to emit light based on the driving current; and a sensing transistor configured to electrically connec

Assignees

• Samsung Display Co Ltd

Inventors

• Song Jun-Yong
• Kwon Oh-Jo
• Kim Ji-Woong
• Shin Choong-Sun
• Ahn Hee-Sun

Classifications

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2320/045

  Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title