Pixel circuit configured to control light-emitting element
US-12112706-B2 · Oct 8, 2024 · US
US2016351124A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016351124-A1 |
| Application number | US-201615164704-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 25, 2016 |
| Priority date | May 28, 2015 |
| Publication date | Dec 1, 2016 |
| Grant date | — |
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An organic light emitting display comprises a display panel having a plurality of pixels, a gate drive circuit that drives scan lines and emission lines on the display panel, and a data drive circuit that drives data lines on the display panel, (n−1)th and nth pixels arranged in a row, a transistor array having a driving transistor, a sampling transistor, and a first initial transistor, and a capacitor connected between an initial voltage input terminal and the sampling transistor. A gate electrode of the first initial transistor for initializing the driving transistor of the nth pixel is connected to a scan line in the (n−1)th pixel.
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What is claimed is: 1 . An organic light emitting display comprising: a display panel having a plurality of pixels; a gate drive circuit that drives scan lines and emission lines on the display panel; and a data drive circuit that drives data lines on the display panel, wherein each of the pixels arranged in an nth row (n is a natural number) comprises: an organic light emitting diode having an anode connected to a node C and a cathode connected to a low-level driving voltage input terminal, a driving transistor having a gate electrode connected to a node A, a source electrode connected to a node D, and a drain electrode connected to a node B, the driving transistor controlling a driving current applied to the organic light emitting diode, a first transistor that is connected between a data line and the node D, a second transistor that is connected between the node D and a high-level driving voltage input terminal, a third transistor that is connected to the node A and the node B, a fourth transistor that is connected to the node B and the node C, a fifth transistor that is connected between the node A and an initial voltage input terminal, and a capacitor that is connected between the node A and the initial voltage input terminal. 2 . The organic light emitting display of claim 1 , wherein one frame comprises an initial period in which the node A is initialized, a sampling period in which a threshold voltage of the driving transistor is sampled and stored at the node A, an emission period in which a source-gate voltage of the driving transistor is programmed to have the sampled threshold voltage, and the organic light emitting diode emits light by a driving current corresponding to the programmed source-gate voltage, wherein a gate electrode of the fifth transistor is connected to an (n−1)th scan line to which an (n−1)th scan signal is applied, a gate electrode of the first transistor and a gate electrode of the third transistor are connected to an nth scan line to which an nth scan signal is applied, and a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to an nth emission line to which an nth emission signal is applied, wherein in the initial period, the (n−1)th scan signal is applied at an ON level, and the nth scan signal and the nth emission signal are applied at an OFF level, wherein in the sampling period, the nth scan signal is applied at the ON level, and the (n−1)th scan signal and the nth emission signal are applied at the OFF level, and wherein in the emission period, the nth emission signal is applied at the ON level, and the (n−1)th scan signal and the nth scan signal are applied at the OFF level. 3 . The organic light emitting display of claim 1 , further comprising a sixth transistor connected between the initial voltage input terminal and the node C. 4 . The organic light emitting display of claim 3 , wherein one frame comprises an initial period in which the node A and the node C are initialized, a sampling period in which a threshold voltage of the driving transistor is sampled and stored at the node A, an emission period in which a source-gate voltage of the driving transistor is programmed to have the sampled threshold voltage, and the organic light emitting diode emits light by a driving current corresponding to the programmed source-gate voltage, wherein a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to an (n−1)th scan line to which an (n−1)th scan signal is applied, a gate electrode of the first transistor and a gate electrode of the third transistor are connected to an nth scan line to which an nth scan signal is applied, and a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to an nth emission line to which an nth emission signal is applied, wherein in the initial period, the (n−1)th scan signal is applied at an ON level, and the nth scan signal and the nth emission signal are applied at an OFF level, wherein in the sampling period, the nth scan signal is applied at the ON level, and the (n−1)th scan signal and the nth emission signal are applied at the OFF level, and wherein in the emission period, the nth emission signal is applied at the ON level, and the (n−1)th scan signal and the nth scan signal are applied at the OFF level. 5 . The organic light emitting display of claim 3 , wherein one frame comprises an initial period in which the node A and the node C are initialized, a sampling period in which a threshold voltage of the driving transistor is sampled and stored at the node A, an emission period in which a source-gate voltage of the driving transistor is programmed to have the sampled threshold voltage, and the organic light emitting diode emits light by a driving current corresponding to the programmed source-gate voltage, wherein a gate electrode of the fifth transistor is connected to an (n−1)th scan line to which an (n−1)th scan signal is applied, a gate electrode of the first transistor, a gate electrode of the third transistor, and a gate electrode of the sixth transistor are connected to an nth scan line to which an nth scan signal is applied, and a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to an nth emission line to which an nth emission signal is applied, wherein in the initial period, the (n−1)th scan signal is applied at an ON level, and the nth scan signal and the nth emission signal are applied at an OFF level, wherein in the sampling period, the nth scan signal is applied at the ON level, and the (n−1)th scan signal and the nth emission signal are applied at the OFF level, and wherein in the emission period, the nth emission signal is applied at the ON level, and the (n−1)th scan signal and the nth scan signal are applied at the OFF level. 6 . The organic light emitting display of claim 2 wherein the initial period is included in an (n−1)th horizontal period, and the sampling period is included in an nth horizontal period. 7 . The organic light emitting display of claim 1 , wherein, in each pixel, each transistor whose source electrode or drain electrode is connected to one electrode of the capacitor comprises at least two series-connected transistors, which are switched on by a same control signal. 8 . The organic light emitting display of claim 3 , wherein a first electrode of the capacitor is positioned between insulating layers that are disposed between a semiconductor layer and a source electrode of the fifth transistor, and the first electrode of the capacitor is connected via a contact hole to a drain electrode of the fifth transistor and to a drain electrode of the sixth transistor. 9 . The organic light emitting display of claim 1 , further comprising a metal layer under a semiconductor layer of the driving transistor. 10 . The organic light emitting display of claim 1 , wherein a first electrode of the capacitor that receives an initial voltage from the initial voltage input terminal is disposed corresponding to the gate electrode of the driving transistor. 11 . The organic light emitting display of claim 1 , wherein a first electrode of the capacitor that receives an initial voltage from the initial voltage input terminal is disposed in an area corresponding to a semiconductor layer of the third transistor that operates during a sampling period. 12 . The organic light emitting display of claim 1 , wherein a first electrode of the capacitor is the gate electrode of the driving transistor connected to the node A, a second electrode of the capacitor corresponds to a
the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror · CPC title
in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title
Preventing or counteracting the effects of ageing · CPC title
Precharge or discharge of pixel before applying new pixel voltage · CPC title
using an active matrix · CPC title
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