Method and system for generating a ramping signal

Patent metadata

Field	Value
Publication number	US-10992893-B2
Application number	US-201916527661-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Dec 12, 2013
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

First claim

What is claimed is:

1. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate an enable signal according to a first clock signal;
a plurality of current generating circuits, each configured to generate a respective first current based on a respective output of a respective storage circuit; and
an offset circuit configured to generate an offset current according to a second clock signal, the frequency of one of the first and second clock signals being a multiple of a frequency of the other of the first and second clock signals;
wherein the ramping signal is based on the first currents and the offset current.

2. The system of claim 1 , further comprising:
a load block configured to generate the ramping signal based on the first currents and the offset current.

3. The system of claim 2 , wherein:
the load block is further configured to generate a first voltage based on the first currents, the first voltage having a staircase shape, the staircase shape having a step size, wherein the ramping signal is based on the first voltage and the offset current.

4. The system of claim 3 , wherein:
the offset current has a square wave form;
the load block is further configured to generate an offset voltage based on the offset current, the offset voltage having a size that is half of the step size of the staircase shape of the first voltage; and
the ramping signal is based on the first voltage and the offset voltage.

5. The system of claim 4 , wherein:
a step duration of the staircase shape is substantially the same as a period of the square wave form.

6. The system of claim 1 , wherein a slope of the ramping signal is adjustable based on adjusting the frequency of the first clock signal.

7. The system of claim 1 , wherein each of the storage circuits includes a latch, and wherein a first latch receives the enable signal.

8. The system of claim 7 , wherein the latches are gated D latches or edge triggering registers.

9. The system of claim 1 , wherein each of the first current generating circuits includes one or more transistors, and a gate of one transistor is coupled to an output of the corresponding storage circuit to receive the propagated first enable signal.

10. The system of claim 9 , further comprising:
one or more comparators each coupled to a column read circuit of an image sensor to receive a readout signal, wherein the comparator compares the readout signal with the ramping signal.

11. The system of claim 10 , further comprising:
a counter coupled to the comparator, wherein the counter records a value corresponding to the ramping signal when the comparator switches its comparing result.

12. The system of claim 1 , wherein each of the current generating circuits includes one or more transistors, and a gate of one transistor is coupled to an output of the corresponding storage circuit to receive the enable signal.

13. The system of claim 12 , further comprising:
a control circuit block;
wherein:
the load block is coupled to the current generating circuits, and includes one or more resistors configured to convert the first currents and the offset current to a ramping voltage signal, and
the control circuit block is configured to control a total equivalent resistance of the one or more resistors.

14. A method for generating a ramping signal comprising:
applying an enable signal to a series of storage circuits, each of the storage circuits including an input and an output, the output of a previous storage circuit being coupled to the input of a next storage circuit;
applying a first clock signal to the series of storage circuits, wherein the first clock signal enables the series of storage circuits to propagate the enable signal through the series of storage circuits;
generating a respective first current based on the respective output of the respective storage circuit;
generating an offset current according to a second clock signal, the frequency of one of the first and second clock signals being a multiple of a frequency of the other of the first and second clock signals;
wherein the ramping signal is based on the first currents and the offset current.

15. The method of claim 14 , further comprising:
generating the ramping signal based on the first currents and the offset current.

16. The method of claim 15 , further comprising:
generating a first voltage based on the first currents, the first voltage having a staircase shape, the staircase shape having a step size, wherein the ramping signal is based on the first voltage and the offset current.

17. The method of claim 16 , further comprising:
generating an offset voltage based on the offset current, wherein the offset current has a square wave form, the offset voltage has a size that is half of the step size of the staircase shape of the first voltage, and the ramping signal is based on the first voltage and the offset voltage.

18. The method of claim 17 , wherein:
a step duration of the staircase shape is substantially the same as a period of the square wave form.

19. The method of claim 14 , wherein a slope of the ramping signal is adjustable based on adjusting the frequency of the first clock signal.

20. The method of claim 14 , further comprising:
comparing a readout signal of an image sensor with the ramping signal; and
recording a value corresponding to the ramping signal when a result of the comparing changes.

Assignees

• Cista Sys Corp

Inventors

• Lee Dennis Tunglin
• Zhang Guangbin

Classifications

• H03K4/02 Primary

  having stepped portions, e.g. staircase waveform · CPC title

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H04N25/673

  by using reference sources · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title