Three-dimensional memory device with mobility-enhanced vertical channels and methods of forming the same

Patent metadata

Field	Value
Publication number	US-10985172-B2
Application number	US-201916251854-A
Country	US
Kind code	B2
Filing date	Jan 18, 2019
Priority date	Jan 18, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

First claim

What is claimed is:

1. A method of forming a three-dimensional memory device, comprising:
providing a combination of an alternating stack of insulating layers and electrically conductive layers overlying a substrate and a memory opening fill structure that vertically extends through the alternating stack, wherein the memory opening fill structure comprises a memory film, a vertical semiconductor channel, and a core structure comprising a core material, wherein the core material comprises a phase change material having a first phase state that is an amorphous state and a second phase state that is a polycrystalline state, and the phase change material is a dielectric material having an electrical conductivity less than 1.0×10 −5 S/m in the amorphous state and in the polycrystalline state; and
inducing a volume expansion in the core material by performing an anneal process that induces a microstructural change within the core material during conversion of the phase change material from the amorphous state to the polycrystalline state, wherein the volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel, and a lower end of the vertical semiconductor channel extends beneath a lower end of the core structure;
wherein: the lateral compressive strain has a magnitude in a range from 0.1 to 2.0% in the vertical semiconductor channel: and the vertical tensile strain has a magnitude in a range from 0.01% to 0.2% in the vertical semiconductor channel;
wherein the core material includes a compound comprising germanium, tellurium, and oxygen; and
wherein the core material comprises oxygen at an atomic percentage in a range from 6.0% to 14%, such that the phase change material remains as the dielectric material in the polycrystalline state.

2. The method of claim 1 , wherein the core material changes from the first phase state to the second phase state during the anneal process.

3. The method of claim 2 , wherein:
the amorphous state has a first density; and
the polycrystalline state has a second density that is less than the first density.

4. The method of claim 3 , wherein the second density is in a range from 90% of the first density to 98% of the first density.

5. The method of claim 1 , wherein the core structure has a vertical-to-lateral dimension ratio in a range from 3 to 300.

6. The method of claim 1 , wherein the anneal process is performed at an elevated temperature in a range from 400 degrees Celsius to 1,100 degrees Celsius.

7. The method of claim 1 , further comprising:
forming an in-process alternating stack of the insulating layers and sacrificial material layers over the substrate;
forming a memory opening through the in-process alternating stack;
forming the memory opening fill structure in the memory opening; and
replacing the sacrificial material layers with the electrically conductive layers, wherein the alternating stack of the insulating layers and the electrically conductive layers is provided.

8. The method of claim 7 , wherein forming the memory opening fill structure comprises:
forming the memory film on a sidewall of the in-process alternating stack in the memory opening;
forming the vertical semiconductor channel on the memory film;
forming the core structure on the vertical semiconductor channel; and
forming a drain region comprising a doped semiconductor material over the core structure and on an upper end of the vertical semiconductor channel.

9. The method of claim 1 , wherein:
the three-dimensional memory device comprises a terrace region in which the electrically conductive layers have a respective lateral extent that decreases with a vertical distance from the substrate; and
the method comprises:
forming a retro-stepped dielectric material portion over the alternating stack in the terrace region; and
forming word line contact via structures that contact a respective one of the electrically conductive layers through the retro-stepped dielectric material portion after performing the anneal process.

Assignees

• Sandisk Technologies Llc

Inventors

• Ge Chun
• Zhang Yanli
• Zhou Fei
• Makala Raghuveer S

Classifications

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D30/6893

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title