Die processing

Patent metadata

Field	Value
Publication number	US-10985133-B2
Application number	US-202016910432-A
Country	US
Kind code	B2
Filing date	Jun 24, 2020
Priority date	Apr 21, 2017
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

First claim

What is claimed is:

1. A method comprising:
applying, to a substrate including a wafer, a protective layer to a bonding surface of the wafer;
singulating the wafer and the protective layer into a plurality of semiconductor die components; and
removing the protective layer to expose an individual bonding surface of one or more semiconductor die components of the plurality of semiconductor die components.

2. The method of claim 1 , further comprising:
cleaning the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

3. The method of claim 2 , wherein cleaning the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components comprises mechanically cleaning the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

4. The method of claim 2 , wherein cleaning the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components comprises chemically cleaning the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

5. The method of claim 2 , wherein cleaning the individual bonding surface of one or more semiconductor die components of the plurality of semiconductor die components comprises wet cleaning the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

6. The method of claim 1 , further comprising:
plasma-activating the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

7. The method of claim 1 , further comprising:
stretching a carrier coupled to the substrate to form gaps between the one or more semiconductor die components of the plurality of semiconductor die components fixed to the carrier; and
perforating the carrier along one or more of the gaps.

8. The method of claim 7 , wherein perforating the carrier along the one or more of the gaps comprises perforating the carrier along the one or more of the gaps using one or more of a dicing blade, a hot knife, or an optical knife.

9. The method of claim 7 , further comprising:
cleaning one or more edges of the one or more semiconductor die components of the plurality of semiconductor die components while the one or more semiconductor die components of the plurality of semiconductor die components are fixed to the carrier, the edges being exposed in the one or more of the gaps.

10. The method of claim 7 , wherein the carrier comprises a dicing sheet.

11. The method of claim 1 , wherein the protective layer is a first protective layer on a first bonding surface of the wafer and the substrate comprises a second protective layer on a second bonding surface of the wafer, the second bonding surface being different than the first bonding surface and the method further comprising:
removing the second protective layer after singulating the wafer into the plurality of semiconductor die components.

12. A method comprising:
applying, to a substrate including a wafer, a protective layer to a bonding surface of the wafer, the substrate being coupled to a carrier;
singulating the wafer and the protective layer into a plurality of semiconductor die components;
stretching the carrier to form gaps between one or more semiconductor die components of the plurality of semiconductor die components fixed to the carrier; and
after stretching the carrier, removing the protective layer to expose an individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

13. The method of claim 12 , further comprising:
plasma-activating the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components.

14. The method of claim 12 , further comprising:
perforating the carrier along one or more of the gaps.

15. The method of claim 14 , wherein perforating the carrier along the one or more of the gaps comprises perforating the carrier along the one or more of the gaps using one or more of a dicing blade, a hot knife, or an optical knife.

16. The method of claim 14 , further comprising:
cleaning the individual bonding surface of the one or more semiconductor die components of the plurality of semiconductor die components; and
cleaning edges of the one or more semiconductor die components of the plurality of semiconductor die components, the edges being exposed in the gaps.

17. The method of claim 16 wherein cleaning the individual bonding surface of one or more semiconductor die components of the plurality of semiconductor die components comprises at least one of (i) mechanically cleaning the individual bonding surface, (ii) chemically cleaning the individual bonding surface, or (iii) wet cleaning the individual bonding surface.

18. The method of claim 12 , wherein the protective layer is a first protective layer on a first bonding surface of the wafer and the substrate comprises a second protective layer on a second bonding surface of the wafer, the second bonding surface being different than the first bonding surface and the method further comprising:
removing the second protective layer after singulating the wafer into the plurality of semiconductor die components.

Assignees

• Invensas Bonding Tech Inc

Inventors

• Uzoh Cyprian Emeka

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title