Single metallization scheme for gate, source, and drain contact integration

Patent metadata

Field	Value
Publication number	US-10985076-B2
Application number	US-201816112092-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	Aug 24, 2018
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming one or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates;
forming source and drain (S/D) contacts, at least one material of the S/D contacts being formed in the PFET gates;
depositing insulating material as self-aligned caps directly above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts, the self-aligned caps directly above the NFET gates being formed to a width of the NFET gates; and
forming middle of the line (MOL) contacts above the S/D contacts.

2. The method of claim 1 , wherein the NFET gates comprise at least one or more N-type work function metals and at least one or more P-type work function metals.

3. The method of claim 1 , wherein the PFET gates comprise at least one or more P-type work function metals along with the at least one material of the S/D contacts.

4. The method of claim 1 , wherein the at least one material of the S/D contacts comprises a S/D contact liner.

5. The method of claim 1 , wherein the at least one material of the S/D contacts comprises titanium.

6. The method of claim 1 , wherein the at least one material of the S/D contacts comprises titanium along with a selection from the group consisting of titanium nitride and carbide.

7. The method of claim 1 , wherein the at least one material of the S/D contacts is pinched off in the PFET gates so as to fill in a void in at least one or more P-type work function metals of the PFET gates.

8. The method of claim 7 , wherein a block mask material filled in the void in the at least one or more P-type work function metals of the PFET gates prior to forming the at least one material of the S/D contacts.

9. The method of claim 1 , wherein the S/D contacts are formed over epitaxial S/D regions.

10. The method of claim 1 , wherein the insulating material is formed as the insulator portions adjacent to the S/D contacts by:
recessing a S/D contact liner of the S/D contacts to create recessed areas while not recessing a S/D contact metal of the S/D contacts; and
depositing the insulating material in the recessed areas, thereby forming insulator portions adjacent to the S/D contact metal.

11. The method of claim 1 , wherein materials of the NFET gates and the PFET gates are recessed while recessing a S/D contact liner of the S/D contacts.

12. The method of claim 11 , wherein the materials of the NFET and PFET gates are recessed more than the S/D contact liner of the S/D contacts.

13. The method of claim 1 , wherein the self-aligned caps are formed directly on the NFET gates.

Assignees

• IBM

Inventors

• Greene Andrew
• Chan Victor W C
• Muthinti Gangadhara Raja

Classifications

• H10D64/01354

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title