Trench silicide contacts with high selectivity process

Patent metadata

Field	Value
Publication number	US-9923078-B2
Application number	US-201514928719-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

First claim

The invention claimed is:

1. A method for forming self-aligned contacts, comprising:
etching a cut region through a first dielectric layer between fin regions of a semiconductor device down to a substrate;
filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer;
planarizing the first material and stopping on the first dielectric layer to form a planar surface of the first material;
forming and patterning a second dielectric layer above the planar surface to expose portions of the first dielectric layer;
isotropic etching the first dielectric layer to expose source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are exposed, the isotropic etching being super selective with an etch ratio of 100:1 or greater to remove the first dielectric layer relative to the first material, the second dielectric layer and gate structures, the gate structures being disposed between the source and drain regions;
depositing metal in the trenches to form contacts to the source and drain regions; and
replacing the second dielectric layer with a second dielectric material.

2. The method as recited in claim 1 , wherein isotropic etching includes one of a buffered hydrofluoric (BHF) etch or a chemical oxide removal (COR) process.

3. The method as recited in claim 1 , wherein the first dielectric layer includes a silicon oxide and the first material includes a silicon nitride.

4. The method as recited in claim 1 , wherein the contacts have a first width at a first position in contact with the source and drain regions that is larger than a second width at a second position higher than the first position up to a surface of the first material.

5. The method as recited in claim 1 , wherein the contacts include lateral sides below a surface of the first material that forms an angle of less than 90 degrees from vertical.

6. The method as recited in claim 1 , wherein the second dielectric material includes amorphous carbon.

7. The method as recited in claim 1 , wherein the contacts include a first portion up to a height of the gate structures and an extended portion that extends above the gate structures.

8. The method as recited in claim 7 , wherein the extended portions are separated by the second dielectric material.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Greene Andrew M
• Pranatharthiharan Balasubramanian
• Xie Ruilong

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/0698

  Local interconnections · CPC title