Method for orienting solder balls on a BGA device

US10980134B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10980134-B2
Application numberUS-201916372268-A
CountryUS
Kind codeB2
Filing dateApr 1, 2019
Priority dateSep 28, 2012
Publication dateApr 13, 2021
Grant dateApr 13, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1. A device, comprising: a printed circuit board (PCB) having a land surface; a package substrate having a mounting surface and a die side surface opposite the mounting surface; and a first plurality and a second plurality of solder balls electrically joining the mounting surface of the package substrate to the land surface of the PCB, the first plurality of solderballs having a first average diameter, and the second plurality of solder balls having a second average diameter, wherein the first average diameter is larger than the second average diameter. 2. The device of claim 1 , wherein the land surface of the PCB has one or more recesses beneath the first plurality of solderballs, and the mounting surface of the package substrate has one or more recesses over the first plurality of solderballs, and wherein the land surface of the PCB has one or more recesses beneath the second plurality of solderballs, and the mounting surface of the package substrate does not include a recess over the second plurality of solderballs. 3. The device of claim 1 , wherein the land surface of the PCB has one or more recesses beneath the first plurality of solderballs, and the mounting surface of the package substrate has one or more recesses over the first plurality of solderballs, and wherein the land surface of the PCB is does not include a recess beneath the second plurality of solderballs, and the mounting surface of the package substrate has one or more recesses over the second plurality of solderballs. 4. The device of claim 1 , wherein the first average diameter is at least 10% greater than the second average diameter. 5. The device of claim 1 , further comprising: a die mounted on the die side surface of the package substrate. 6. The device of claim 5 , wherein the die has a die area, wherein the mounting surface of the package substrate has a die shadow area aligned with the die area, and wherein the first plurality of solder balls is disposed within the die shadow area. 7. The device of claim 6 , wherein the second plurality of solder balls is disposed in a region surrounding the die shadow area. 8. The device of claim 7 , wherein the mounting surface of the package substrate is has four corner areas, and wherein the first plurality of solder balls is further disposed in the corner areas. 9. The device of claim 1 , further comprising: a third plurality of solder balls electrically joining the mounting surface of the package substrate to the land surface of the PCB, the third plurality of solderballs having a third average diameter, wherein the third average diameter is different than the first average diameter and different than the second average diameter.

Assignees

Inventors

Classifications

  • characterised by changes in properties of the bump connectors during connecting · CPC title

  • Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

  • Manufacturing or production processes characterised by the final manufactured product · CPC title

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What does patent US10980134B2 cover?
A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated b…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H05K3/3436. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 13 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).