Smart Skip Verify Mode For Programming A Memory Device
US-2017125117-A1 · May 4, 2017 · US
Dynamic bit-scan techniques for memory device programming
US10971222B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10971222-B2 |
| Application number | US-201916717532-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 17, 2019 |
| Priority date | Jun 5, 2018 |
| Publication date | Apr 6, 2021 |
| Grant date | Apr 6, 2021 |
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- Title
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Abstract
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An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.
First claim
Opening claim text (preview).
The invention claimed is: 1. An apparatus comprising: a plurality of memory cells; a programming circuit configured to apply a plurality of programming pulses to the memory cells; and a scanning circuit configured to repeatedly switch between: performing an n-state bitscan after each of multiple programming pulses until first predetermined criteria are satisfied; and performing an m-state bitscan after each of multiple programming pulses until second predetermined criteria are satisfied, where m>n, and n>0. 2. The apparatus of claim 1 , wherein the first predetermined criteria comprises passing the n-state bitscan, and the second predetermined criteria comprises passing the m-state bitscan. 3. The apparatus of claim 2 , wherein: passing the n-state bitscan comprises determining that a number of memory cells that have not been programmed to a desired memory state is less than a predetermined value for each of n memory states; and passing the m-state bitscan comprises determining that the number of memory cells that have not been programmed to a desired memory state is less than the predetermined value for each of m memory states. 4. The apparatus of claim 1 , wherein: performing an n-state bitscan comprises determining a number of memory cells that have not been programmed to a desired memory state for each of n memory states; and performing an m-state bitscan comprises determining a number of memory cells that have not been programmed to a desired memory state for each of m memory states. 5. The apparatus of claim 1 , further comprising: a first counting circuit configured to count a number of memory cells that have not been programmed to a desired memory state for each of n memory states; and a second counting circuit configured to count a number of memory cells that have not been programmed to a desired memory state for each of m memory states. 6. The apparatus of claim 5 , wherein the first counting circuit and second counting circuit are each configured to collectively count memory cells for all memory states. 7. The apparatus of claim 5 , wherein the first counting circuit and second counting circuit are each configured to separately count memory cells for each memory state.
Assignees
Inventors
Classifications
Response verification devices · CPC title
using charge trapping in an insulator · CPC title
- G11C11/5628Primary
Programming or writing circuits; Data input circuits · CPC title
Word line control · CPC title
Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title
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- What does patent US10971222B2 cover?
- An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pul…
- Who is the assignee on this patent?
- Sandisk Technologies Llc
- What technology area does this patent fall under?
- Primary CPC classification G11C11/5628. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).