State-dependent lockout in non-volatile memory

Patent metadata

Field	Value
Publication number	US-9437302-B2
Application number	US-201514616309-A
Country	US
Kind code	B2
Filing date	Feb 6, 2015
Priority date	Feb 6, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.

First claim

What is claimed is:

1. A method of program verification in non-volatile storage, comprising:
pre-charging a sense node of a plurality of sense amplifiers to a sense level for sensing at a first verify level corresponding to a selected state, the plurality of sense amplifiers are coupled to a plurality of bit lines associated with a plurality of non-volatile storage elements coupled to a first word line, each bit line is associated with a set of user data latches;
determining for each bit line whether a corresponding set of user data latches indicate the selected state;
for each set of user data latches that does not indicate the selected state, discharging a corresponding sense node from the sense level; and
for each set of user data latches that indicates the selected state, sensing at the first verify level using the sense level at the corresponding sense node.

2. The method of claim 1 , further comprising:
determining by a first latch scan circuit whether the program data in the set of user data latches matches the selected state.

3. The method of claim 2 wherein determining whether the program data matches the selected state comprises selecting the program data from the set of user data latches using a coding for the selected state.

4. The method of claim 3 , wherein determining whether the program data matches the selected state comprises:
combining the output of each user data latch using the first latch scan circuit to generate a first logic value when each user data latch matches the coding for the selected state; and
combining the output of each user data latch using the first latch scan circuit to generate a second logic value when each user data latch does not matching the coding for the selected state.

5. The method of claim 4 , wherein:
each user data latch of each set includes an output coupled to a bus;
the first latch scan circuit of each sense amplifier includes an upper node coupled to the sense node of the sense amplifier; and
the first latch scan circuit includes a first transistor having a gate connected to the bus.

6. The method of claim 1 , further comprising:
storing in a first data latch a first value based on sensing at the first verify level for the selected state.

7. The method of claim 6 , wherein:
sensing at the first verify level comprises detecting a voltage at the sense node based on a conductivity of the non-volatile storage element;
the method further comprises, combining a strobe of the sense node voltage with a previous value stored in the first data latch to generate the first value.

8. The method of claim 7 , further comprising:
sensing at a second verify level corresponding to the selected state after sensing at the first verify level;
wherein sensing at the first verify level determines a voltage level of the sense node a first time after applying a final verify voltage to the first word line; and
wherein sensing at the second verify level determines the voltage level of the sense node a second time after applying the final verify voltage to the first word line, the second time is after the first time.

9. The method of claim 8 , further comprising:
strobing a result of sensing at the second verify level to a second data latch;
combining the result of sensing at the second verify level with an output of each user data latch to generate updated program data; and
storing the updated program data in the set of user data latches.

10. The method of claim 9 , further comprising:
after sensing completes for all of a plurality of states including the selected state;
scanning an output of each user data latch to determine a program enable/inhibit value;
storing the program enable/inhibit value in the second data latch;
after setting a bit line voltage based on the program enable/inhibit value, transferring the first value from the first data latch to the second data latch.

11. The method of claim 10 , further comprising:
setting the bit line voltage based on the program enable/inhibit value in the second data latch;
wherein setting the bit line voltage comprises charging the bit line to a program inhibit level if the program enable/inhibit value indicates program inhibit; and
wherein setting the bit line voltage comprises discharging the bit line to a program enable level if the program enable/inhibit value indicates program enable.

12. The method of claim 11 , further comprising after transferring the first value from the first data latch to the second data latch:
charging the bit line from the program enable level to a reduced programming level if the second data latch indicates reduced programming; and
maintaining the bit line at the program enable level if the second data latch does not indicate reduced programming.

13. A sense amplifier circuit, comprising:
a bus;
a set of user data latches configured to receive program data for programming to a non-volatile storage element, the set of user data latches each having an output coupled to the bus;
an internal sense node selectively connectable to a first bit line in communication with the non-volatile storage element, the internal sense node charges to a sense level during program verification for a selected state; and
a first latch scan circuit having a first node connected to the internal sense node and a first switch having a gate connected to the bus, wherein the first latch scan circuit drains the sense node from the sense level prior to sensing when the program data in the set of user data latches does not match the selected state.

14. The sense amplifier circuit of claim 13 , wherein:
when the program data in the set of user data latches matches the selected state, the sense node remains at the sense level when sensing for the selected state begins; and
a voltage develops at the sense node based on a conductivity of the non-volatile storage element when sensing for the selected state.

15. The sense amplifier circuit of claim 13 , further comprising:
a first data latch having an output coupled to the bus;
the first data latch stores a value after sensing for the selected state based on the voltage developed at the sense node.

16. The sense amplifier circuit of claim 15 , wherein:
the value stored in the first data latch is based on a combination of the voltage developed at the sense node and a previous value stored in the first data latch.

17. The sense amplifier circuit of claim 16 , further comprising:
a set of latch scan circuits including the first latch scan circuit, the set of latch scan circuits combines the previous value stored in the first data latch and the voltage developed at the sense node using a logic AND operation.

18. The sense amplifier circuit of claim 13 , wherein:
the first latch scan circuit selects the program data from the set of user data latches using a coding for the selected state.

19. The sense amplifier circuit of claim 18 , wherein:
the sense amplifier combines the output of each user data latch using the first latch scan circuit to generate a first logic value when each user data latch matches the coding for the selected state; and
the sense amplifier combines the output of each user data latch using the first latch scan circuit to generate a second logic value when each user data latch does not match the coding for the selected state.

20. The sense amplifier circuit of claim 13 , further comprising:
a three-dimensional array of non-volatile storage elements including the non-volatile storage element.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Tseng Tai-Yuan
• Hsu Cynthia
• Kim Kwang Ho

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title