Sense amplifier with efficient use of data latches

Patent metadata

Field	Value
Publication number	US-9552882-B2
Application number	US-201514616289-A
Country	US
Kind code	B2
Filing date	Feb 6, 2015
Priority date	Feb 6, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.

First claim

What is claimed is:

1. A non-volatile storage device, comprising:
a set of user data latches configured to receive program data for programming to a non-volatile storage element, the set of user data latches are configured to update based on sensing at a plurality of final verify levels corresponding to a plurality of physical states during program verification;
a first data latch selectively connectable to one or more bit lines in communication with the non-volatile storage element for setting a bit line voltage level during programming, the first data latch configured to update with a first value based on sensing at a plurality of first verify levels corresponding to the plurality of states and to set an initial voltage level on the one or more bit lines for a program pulse based on the set of user data latches; and
a sense node selectively connectable to the one or more bit lines and configured to store a second value based on a threshold voltage of the non-volatile storage element during sensing, the sense node configured to temporarily store the first value from the first data latch after sensing at the plurality of the first verify levels and to selectively change the initial voltage level on the one or more bit lines for the program pulse based on the first value.

2. The non-volatile storage device of claim 1 , further comprising:
a bus connected to the first data latch and the sense node, the bus transfers the-first value from the first data latch to the sense node after sensing at the plurality of first verify levels;
wherein the bus transfers a result of scanning an output of the user data latches for program enable or program inhibit to the first data latch after transferring the first value;
wherein the first data latch sets the initial voltage level on the one or more bit lines based on scanning the output of the user data latches.

3. The non-volatile storage device of claim 2 , further comprising:
a first scan circuit comprising a first switch and a second switch connected in series, the first switch is connected to the sense node, the second switch includes a gate connected to the bus whereby the first scan circuit generates a value based on a logic combination of the sense node and the bus.

4. The non-volatile storage device of claim 3 , further comprising:
a second data latch selectively connectable to the one or more bit lines, the second data latch stores a first result of sensing at each low verify level;
wherein the second data latch includes an output that is scanned with an output of each data latch after sensing at each low verify level to generate the first value.

5. The non-volatile storage device of claim 4 , further comprising:
a first scan circuit having a first node connected to the second data latch, a second node connected to a low-level voltage, and a first transistor having a gate connected to the bus.

6. The non-volatile storage device of claim 5 , wherein:
the first scan circuit provides a state-specific result as the first value when the set of user data latches matches a state currently being sensed; and
the state-specific result is stored in the first data latch.

7. The non-volatile storage device of claim 6 , wherein:
the first data latch after first level sensing for a second state includes the state-specific result for a first state; and
the state-specific result for the first state is combined with a result of scanning the output of the second data latch and the set of user data latches after low level sensing for the second state.

8. The non-volatile storage device of claim 7 , wherein:
the state-specific result for the first state is combined with the result of scanning using a logic OR operation to maintain the state-specific result for the first state when the first state is a targeted state and the second state is a non-targeted state.

9. The non-volatile storage device of claim 1 , further comprising:
a three-dimensional array of non-volatile storage elements including the non-volatile storage element.

10. A method of operating non-volatile storage, comprising:
storing in a first data latch a first value based on scan operations from sensing at a low verify level for a plurality of physical states;
storing in a set of user data latches a second value based on scan operations from sensing at a high verify level for the plurality of physical states;
transferring the first value to a temporary node;
updating the first data latch based on the second value;
setting an initial voltage on a bit line after updating the first data latch based on the second value;
updating the first data latch based on the first value after setting the initial voltage; and
selectively updating the initial voltage after updating the first data latch based on the first value.

11. A device, comprising:
a first data latch configured to store first data based on accumulated sense results for a first set of verify levels for a plurality of states;
a set of user data latches configured to store second data based on sensing at a second set of verify levels for the plurality of sates;
a node configured to receive the first data from the first data latch after sensing at the first set of verify levels and the second set of verify levels; and
a bit line configured to receive an initial voltage based on third data stored in the first data latch after storing the first data at the node and to selectively update the initial voltage based on the first data after transferring the first data from the node to the first data latch.

12. The device of claim 11 , wherein:
the first data latch is configured to store the first data from the node after the initial voltage is set for the bit line;
the bit line remains at the initial voltage when the first data stored in the first data latch is a first logic value; and
the bit line is charged to a second voltage that is higher than the initial voltage when the first data stored in the first data latch is a second logic value.

13. The device of claim 11 , further comprising:
a second data latch configured to store a first result based on sensing at a first verify level of the first set; and
a first scan circuit having a node connected to the second data latch, the first scan circuit configured to scan an output of the second data latch with an output of the set of user data latches.

14. The device of claim 13 , wherein:
the first scan circuit scans the output of the second data latch by combining the output of the second data latch with an output of each of the user data latches using a logic AND operation with the first scan circuit.

15. The device of claim 14 , wherein:
the first scan circuit is configured to combine the output of the second data latch with the output of each of the user data latches for each verify level of the first set to provide the first data when the set of user data latches match a state currently being sensed.

16. The device of claim 15 , wherein:
the first scan circuit is configured to combine the first data from a first state with the output of the second data latch in a logic OR operation to maintain the first data from the first state when later sensing at a non-targeted state.

17. The device of claim 16 , wherein:
the second data latch is configured to store a second result of sensing at each of the verify levels of the second set; and
the first scan circuit is configured to scan the output of the second data latch with the output of each of the user data latches after storing the second result for each final verify level.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Tseng Tai-Yuan
• Li Yenlung
• Hsu Cynthia
• Kim Kwang Ho
• Mui Man L

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title