Select gate selective touch up adjustment
US-2026065996-A1 · Mar 5, 2026 · US
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Lin Lei patents
Lin Lei is listed as an inventor on 41 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lin Lei |
| Total patents | 41 |
| First publication | Jul 25, 2019 |
| Latest publication | Mar 5, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Selective media scanning for a virtual block
US-2026066020-A1 · Mar 5, 2026 · US
Program pulse modification
US-2026056671-A1 · Feb 26, 2026 · US
Determining voltage offset for a memory operation using memory bin and memory position
US-2026037145-A1 · Feb 5, 2026 · US
Memory reset read using priority-based block pool
US-2026037424-A1 · Feb 5, 2026 · US
Probablistically determining memory portions for select gate scanning
US-2026037370-A1 · Feb 5, 2026 · US
Efficient empty page scan operations
US-2026031161-A1 · Jan 29, 2026 · US
Dynamic read disturb handling using selective scanning
US-2026024594-A1 · Jan 22, 2026 · US
Defective word line scan
US-2026018225-A1 · Jan 15, 2026 · US
Block family management for a virtual block
US-12511080-B1 · Dec 30, 2025 · US
Recent patents
Latest publications not already listed above.
Power loss error detection using partial block handling
US-12505899-B2 · Dec 23, 2025 · US
Program pulse modification
US-12493415-B2 · Dec 9, 2025 · US
Defective word line based read scan
US-2025356934-A1 · Nov 20, 2025 · US
Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices
US-2025321679-A1 · Oct 16, 2025 · US
Dynamic threshold computation for gate scan
US-2025259691-A1 · Aug 14, 2025 · US
Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices
US-12386515-B2 · Aug 12, 2025 · US
Ndep low stress refresh erase
US-2025251864-A1 · Aug 7, 2025 · US
Dynamically enabling foreground scans of memory blocks
US-2025130894-A1 · Apr 24, 2025 · US
Word line based program voltage adjustment
US-2024420784-A1 · Dec 19, 2024 · US
Nand detect program completion (ndpc) with power off charge loss calibration in a memory sub-system
US-2024371450-A1 · Nov 7, 2024 · US
Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices
US-2024319886-A1 · Sep 26, 2024 · US
Program pulse modification
US-2024248612-A1 · Jul 25, 2024 · US
Power loss error detection using partial block handling
US-2024170090-A1 · May 23, 2024 · US
Biosynthetic heparin
US-2023151400-A1 · May 18, 2023 · US
Biosynthetic heparin
US-11591628-B2 · Feb 28, 2023 · US
Object location tracking
US-11391573-B2 · Jul 19, 2022 · US
Usage-based server load balancing
US-11336718-B2 · May 17, 2022 · US
Coupling capacitance reduction during program verify for performance improvement
US-2021383879-A1 · Dec 9, 2021 · US
Dynamic bit-scan techniques for memory device programming
US-10971222-B2 · Apr 6, 2021 · US
Usage-based server load balancing
US-2020344291-A1 · Oct 29, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 23 |
| Sandisk Technologies Llc | 7 |
| Verizon Patent & Licensing Inc | 6 |
| Rensselaer Polytech Inst | 3 |
| Western Digital Tech Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/26 | 18 |
| G11C16/0483 | 17 |
| G11C16/08 | 12 |
| G11C16/10 | 11 |
| G06F3/0679 | 8 |