Semiconductor device having plural dummy memory cells

Patent metadata

Field	Value
Publication number	US-10964751-B2
Application number	US-201916586140-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Jan 17, 2019
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of word lines disposed on a substrate in which active regions are defined, and extends in a first direction;
a plurality of bit lines disposed on the plurality of word lines and extending in a second direction, perpendicular to the first direction; and
a plurality of memory cells disposed between the plurality of word lines and the plurality of bit lines and each including a data storage pattern, the plurality of memory cells including a plurality of dummy memory cells and a plurality of main memory cells,
wherein an upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.

2. The semiconductor device of claim 1 , wherein:
the plurality of dummy memory cells are connected to a plurality of the word lines; and
a contact plug is configured to connect at least one of the plurality of word lines that the plurality of dummy memory cells are connected thereto to at least one of the active regions.

3. The semiconductor device of claim 1 , wherein:
the plurality of dummy memory cells and the plurality of main memory cells are connected to a plurality of the word lines;
the plurality of word lines that the plurality of dummy memory cells are connected thereto are not connected to the active regions; and
the plurality of word lines that the plurality of main memory cells are connected thereto are connected to at least one of the active regions.

4. The semiconductor device of claim 1 , further comprising:
a first contact plug configured to connect at least one of the plurality of word lines to a portion of circuit wirings; and
a second contact plug configured to connect the portion of circuit wirings to at least one of the active regions.

5. The semiconductor device of claim 4 , further comprising a base insulating layer disposed on the substrate and in contact with the plurality of word lines,
wherein the first and second contact plugs are disposed in the base insulating layer.

6. The semiconductor device of claim 1 , further comprising:
a base insulating layer disposed between the substrate and the plurality of bit lines; and
a plurality of circuit wirings disposed in the base insulating layer.

7. The semiconductor device of claim 1 , wherein the plurality of word lines are spaced apart from each other by a plurality of gap fill patterns comprising an insulating material.

8. The semiconductor device of claim 1 , wherein each of the plurality of memory cells comprises:
a data storage structure and a switching structure disposed on the plurality of word lines,
wherein the data storage structure and the switching structure are electrically connected to each other by an intermediate electrode.

9. The semiconductor device of claim 8 , wherein the switching structure comprises a threshold switching material.

10. The semiconductor device of claim 8 , wherein the data storage structure comprises a lower electrode, the data storage pattern, and an upper electrode,
wherein the data storage pattern comprises a phase change material.

11. A semiconductor device comprising:
a plurality of row lines disposed on a substrate and extending in a first direction, the row lines spaced apart from each other in a second direction, perpendicular to the first direction;
a plurality of column lines disposed on the plurality of row lines, the column lines are spaced apart from each other in the first direction while extending in the second direction; and
a plurality of memory cells disposed between the plurality of row lines and the plurality of column lines and extending in a third direction, perpendicular to the first and second directions, the plurality of memory cells including a plurality of main memory cells and a plurality of dummy memory cells,
wherein at least one of the plurality of dummy memory cells is connected to one of a plurality of active regions defined in the substrate or floats from the plurality of active regions.

12. The semiconductor device of claim 11 , further comprising:
a first contact plug that is configured to connect at least one of the plurality of row lines to a portion of circuit wirings; and
a second contact plug that is configured to connect the portion of circuit wirings to the plurality of active regions.

13. The semiconductor device of claim 11 , wherein:
the plurality of active regions includes p-type and n-type active regions; and
at least one of the plurality of dummy memory cells is connected to the p-type and n-type regions.

14. The semiconductor device of claim 11 , wherein each of the memory cells comprises a lower electrode, a data storage pattern, an intermediate electrode, a switch and an upper electrode, that are disposed on the plurality of row lines,
wherein the data storage pattern comprises a phase change material, and the switch comprises a threshold switching material.

15. The semiconductor device of claim 14 , wherein the lower electrode is electrically connected to one of the plurality of row lines, and the upper electrode is electrically connected to one of the plurality of column lines.

16. A semiconductor device comprising:
a first row line disposed on a substrate and extending in a first direction;
a second row line extending in the first direction and spaced apart from the first row line in a second direction, perpendicular to the first row line;
a column line disposed on the first and second row lines and extending in the second direction;
a first memory cell disposed between the first row line and the column line; and
a second memory cell disposed between the second row line and the column line,
wherein each of the first and second memory cells includes a data storage pattern, wherein a thickness of the data storage pattern of the first memory cell is less than a thickness of the data storage pattern of the second memory cell.

17. The semiconductor device of claim 16 , further comprising:
a third row line disposed on the column line and overlapping the first row line in the first direction; and
a fourth row line disposed on the column line and overlapping the second row line in the second direction.

18. The semiconductor device of claim 16 , wherein the first and second memory cells are connected to one or more active regions defined in the substrate, by a contact structure.

19. The semiconductor device of claim 18 , wherein the contact structure comprises a plurality of contact plugs and circuit wirings disposed in a third direction perpendicular to the first direction and the second direction.

20. The semiconductor device of claim 16 , wherein the first memory cell floats from one or more active regions defined in the substrate, and the second memory cell is connected to the active regions using a contact structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cui Hao
• Park Se Yun
• Park Jong Hyuk
• Yoon Bo Un
• Yoon Il Young

Classifications

• H10N70/826 Primary

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H01L45/06

  Electricity · mapped topic