Dummy bottom electrode in interconnect to reduce CMP dishing

Patent metadata

Field	Value
Publication number	US-9985075-B2
Application number	US-201615345928-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Jul 28, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

The present disclosure relates an integrated circuit (IC). A plurality of metal layers is disposed within an inter-layer dielectric (ILD) material over the substrate. A memory cell is disposed over a first metal layer at a memory region and comprising a bottom electrode directly above a first metal line within the first metal layer and a top electrode separated from the bottom electrode by a resistance switching element. A dummy structure comprises a dummy bottom electrode arranged directly above a second metal line within the first metal layer at a logic region adjacent to the memory region.

First claim

What is claimed is:

1. An integrated circuit (IC) disposed over a substrate, comprising:
a plurality of metal layers disposed within an inter-layer dielectric (ILD) material over the substrate;
a memory cell disposed over a first metal layer at a memory region and comprising a bottom electrode directly above a first metal line within the first metal layer and a top electrode separated from the bottom electrode by a resistance switching element; and
a dummy structure comprising a dummy bottom electrode arranged directly above a second metal line within the first metal layer at a logic region adjacent to the memory region.

2. The IC of claim 1 , wherein the dummy bottom electrode and the bottom electrode are made of the same material as one another.

3. The IC of claim 1 , wherein an upper surface of the dummy bottom electrode is co-planar with an upper surface of the bottom electrode.

4. The IC of claim 1 , further comprising:
a barrier layer disposed between the dummy bottom electrode and the second metal line.

5. The IC of claim 1 , further comprising:
a bottom etch stop layer surrounding the bottom electrode and the dummy bottom electrode; and
a top etch stop layer disposed on the bottom etch stop layer and extending upwardly along sidewalls of the dummy structure and overlying an upper surface of the dummy structure.

6. The IC of claim 5 , further comprising a dielectric mask disposed on the dummy bottom electrode and covered by the top etch stop layer.

7. The IC of claim 5 , further comprising a TEOS (Tetraethyl Orthosilicate) liner conformally disposed over the top etch stop layer.

8. The IC of claim 1 , wherein the memory region comprises a plurality of resistive random access memory (RRAM) cells respectively comprising a bottom electrode and a top electrode separated by a RRAM dielectric layer.

9. The IC of claim 1 , wherein first metal line is laterally aligned with the second metal line.

10. The IC of claim 1 , wherein the dummy structure has a width in a range of from about 200 Å to about 300 Å.

11. An integrated circuit (IC), comprising:
a semiconductor substrate;
an interconnect structure disposed over the semiconductor substrate, the interconnect structure including a plurality of metal layers disposed over one another and isolated from one another by interlayer dielectric (ILD) material;
a memory cell including a top electrode and a bottom electrode arranged between a lower metal layer and an upper metal layer of the interconnect structure; and
a dummy bottom electrode arranged between the lower and upper metal layers, and having an upper surface that is co-planar with the bottom electrode of the memory cell.

12. The IC of claim 11 , further comprising:
a dielectric mask disposed over the dummy bottom electrode and having dummy mask sidewalls aligned to sidewalls of the dummy bottom electrode; and
a silicon carbide layer extending upwardly along sidewalls of the dummy bottom electrode, along sidewalls of the dielectric mask, and overlying an upper surface of the dielectric mask.

13. The IC of claim 12 , where the silicon carbide layer extends upwardly along sidewalls of the bottom electrode, along sidewalls of the top electrode, and overlies an upper surface of the top electrode.

14. The IC of claim 11 , wherein the dummy bottom electrode and bottom electrode comprise titanium nitride (TiN) having a thickness of about 130 Å, and further comprising a barrier layer disposed between the dummy bottom electrode and an underlying metal line comprising tantalum nitride (TaN) with a thickness of about 10 Å.

15. The IC of claim 11 , further comprising a barrier layer disposed between the dummy bottom electrode and an underlying metal line and comprising tantalum (Ta) with a thickness of about 70 Å.

16. An integrated circuit (IC), comprising:
a memory region and a logic region adjacent to the memory region;
a lower metal layer disposed within a lower interlayer dielectric (ILD) layer and an upper metal layer disposed within an upper ILD layer overlying the lower metal layer;
a memory cell arranged within the memory region between the lower metal layer and the upper metal layer, the memory cell comprising a top electrode and a bottom electrode separated by a resistance switching element, wherein the bottom electrode is electrically coupled to the lower metal layer and the top electrode is electrically coupled to the upper metal layer; and
a dummy structure arranged within the logic region and having a lower surface aligned with a lower surface of the memory cell, the dummy structure comprising a dummy bottom electrode and a dummy dielectric mask disposed on the dummy bottom electrode.

17. The IC of claim 16 , wherein the dummy dielectric mask has a sidewall aligned with a sidewall of the dummy bottom electrode.

18. The IC of claim 16 , further comprising:
a top etch stop layer disposed over the lower ILD layer, extending upwardly along sidewalls of the memory cell and the dummy structure, and overlying surfaces of the memory cell and the dummy structure.

19. The IC of claim 18 , wherein the top etch stop layer contacts and covers a top surface of the dummy dielectric mask.

20. The IC of claim 16 , wherein the dummy bottom electrode is coupled to a lower metal line of the lower metal layer, wherein the lower metal line is connected to an upper metal line of the upper metal layer through a conductive via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry-Hak-Lay
• You Wen-Chun

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title