Method of high density memory fabrication

Patent metadata

Field	Value
Publication number	US-9343463-B2
Application number	US-58690009-A
Country	US
Kind code	B2
Filing date	Sep 29, 2009
Priority date	Sep 29, 2009
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

First claim

What is claimed is:

1. An integrated circuit comprising:
a CMOS level including conducting connection pads for forming electrical connections thereto;
a device level including a uniform horizontal array of identical devices having electrical contacts thereto;
a passive interconnect level formed between said CMOS level and said device level wherein said passive interconnect level has an upper surface that is adjacent to and contacts said device level and a lower surface that is adjacent to and contacts said CMOS level and wherein said passive interconnect level contains two arrays of vias, the first array being an array of active vias each of which pass continuously from said upper surface to said lower surface and form an electrically conducting path between said two surfaces; wherein each active via has an electrically contacting portion on said upper surface of said passive interconnect level that forms an electrically conductive connection to one of said electrical contacts of said device level and wherein each said active via also has an electrically contacting portion on said lower surface of said passive interconnect level that forms an electrically conductive connection to one of said conducting connection pads of said CMOS level, whereby each said active via electrically connects one device conducting pad of said device level to one conducting connection pad of said CMOS level, and wherein
said second array of vias is an array of dummy vias, wherein each of said dummy vias has an electrically contacting portion on said upper surface of said passive interconnect level that forms an electrically conductive connection to one of said electrical contacts of said device level but wherein each said dummy via terminates within said passive interconnect level and does not extend to said lower surface and does not make electrical contact to any of said conducting connection pads of said CMOS level; wherein
said electrically contacting portion of each of said active vias and said electrically contacting portion of each of said dummy vias are identical structures and form a uniform regular array of identical structures horizontally disposed on said upper surface of said passive interconnect level and wherein each of said electrical contacts of said device level is contacted by one of said electrically contacting portions and wherein each of said electrically contacting portions contacts one of said electrical contacts of said device level;
whereby said upper surface of said passive interconnect level is rendered flat and free of warpage by virtue of its geometric and structural uniformity
and whereby
said device level is thereby formed on a flat surface.

2. The circuit of claim 1 wherein a small, uniformly patterned layer of buffer material is interposed between each active device and active via and each dummy device and each dummy via thereby enhancing the uniformity of the distribution of vias.

3. The circuit of claim 1 wherein said devices are MRAM memory junctions.

4. The integrated circuit of claim 1 wherein said interconnect level further comprises:
an etch stop layer contacting said CMOS level;
a first dielectric layer formed on said etch stop layer;
a second etch stop layer formed on said first dielectric layer;
a second dielectric layer formed on said second etch stop layer; wherein
said active vias penetrate said two layers of dielectric material and said two etch stop layers; and
said dummy vias penetrate said second dielectric layer and terminate at said second etch-stop layer.

Assignees

• Zhong Tom
• Zhong Adam
• Kan Wai-Ming J
• Torng Chyu-Jiuh
• Headway Technologies Inc

Inventors

• Zhong Tom
• Zhong Adam
• Kan Wai-Ming J
• Torng Chyu-Jiuh

Classifications

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/092 Primary

  by smoothing the dielectric parts · CPC title

• H01L21/7684

  Electricity · mapped topic

• H01L27/105 Primary

  Electricity · mapped topic