Laterally diffused metal oxide semiconductor with gate poly contact within source window

Patent metadata

Field	Value
Publication number	US-10957774-B2
Application number	US-201816127281-A
Country	US
Kind code	B2
Filing date	Sep 11, 2018
Priority date	Dec 29, 2016
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

First claim

What is claimed is:

1. A method for fabricating a power transistor in an integrated circuit,
the method comprising:
diffusing a source region stripe into an epitaxial layer of a semiconductor substrate, and a drain region stripe into the epitaxial layer such that a channel region stripe is located substantially parallel to and between the source region stripe and the drain region stripe;
growing thick oxide islands that overlie the source region stripe;
forming a gate structure that overlies the thick oxide islands;
forming contacts connected to a gate structure over the thick oxide islands; and
forming a conductive gate runner that connects to the contacts of the gate structure over the thick oxide islands.

2. The method of claim 1 , further including diffusing into the substrate a first well having a first conductivity type into which the source region stripe is diffused, and diffusing into the substrate a second well having a second conductivity type into which the drain region stripe is diffused.

3. The method of claim 2 , in which the power transistor is a laterally diffused metal oxide semiconductor device and in which the second well forms a drift region.

4. The method of claim 1 , in which the gate structure comprises polysilicon.

5. The method of claim 1 , wherein the at least one source region stripe has a linear topology.

6. The method of claim 1 , wherein the conductive gate runner includes a metal line oriented perpendicularly to the source region stripe.

7. A method, comprising:
forming plurality of transistor fingers over a semiconductor substrate, including:
forming a plurality of source region stripes;
forming a plurality of drain region stripes substantially parallel to the source region stripes;
forming a plurality of a channel region stripes, each channel region stripe being located between a corresponding source region stripe and a corresponding drain region stripe;
forming a gate oxide that overlies the channel region stripes;
forming over each of the source region stripes a plurality of spaced apart thick oxide islands;
forming a gate structure that overlies the gate oxide and the thick oxide islands;
forming contacts connected to the gate structure over the thick oxide islands; and
forming a conductive gate runner connected to the contacts.

8. The method of claim 7 , in which the gate structure comprises polysilicon.

9. The method of claim 7 , in which the plurality of transistor fingers is part of a laterally diffused metal oxide semiconductor power transistor having an extension of the gate structure connected to the source region stripe.

10. The method of claim 7 , in which the source region stripes have a linear topology.

11. The method of claim 7 , in which the conductive gate runner is arranged perpendicularly to the source region stripe.

12. The method of claim 7 , further including control circuitry that lies within the semiconductor material substrate with at least one output signal coupled to the gate structure.

13. The method of claim 7 , wherein the conductive gate runner is a portion of a metal grid that connects a plurality of contacts connected to the plurality of source region stripes.

14. A method, comprising:
forming first and second doped stripe regions within a semiconductor substrate;
forming an oxide layer over the semiconductor substrate and over the doped stripe regions;
forming a first thick oxide island over the first doped stripe region, the first thick oxide island located between two contacts connected to the first doped stripe region;
forming a first polysilicon stripe over the oxide layer between the first and second doped stripe regions;
forming over the first thick oxide island a first polysilicon extension connected to the first polysilicon stripe;
forming a contact over the thick oxide island that connects to the first polysilicon extension.

15. The method of claim 14 , wherein the first and second doped stripe regions are n-doped regions.

16. The method of claim 15 , wherein the first doped stripe region is located in a p-type doped region of the substrate, and the second doped stripe region is located in an n-type region of the substrate.

17. The method of claim 14 , further comprising;
forming a third doped stripe region, the second doped stripe region being located between the first and third doped stripe regions;
forming a second thick oxide island over the third doped stripe region;
forming a second polysilicon stripe between the second and third doped stripe regions;
forming over the third doped stripe region a second polysilicon extension connected to the second polysilicon stripe;
forming a second contact that connects to the second polysilicon extension; and
forming a metal layer that connects the first contact and the second contact.

18. The method of claim 14 , further comprising forming a thick oxide stripe between the first polysilicon stripe and the second doped stripe region.

19. The method of claim 14 , further comprising:
forming a fourth doped stripe region in the substrate, the first doped stripe region being located between the second and fourth doped stripe regions; and
forming a third polysilicon stripe between the first and fourth doped stripe regions,
wherein the polysilicon extension connects the first and third polysilicon stripes.

20. The method of claim 14 , further comprising forming within the semiconductor substrate control circuitry with at least one output signal coupled to the first polysilicon stripe.

Assignees

• Texas Instruments Inc

Inventors

• Pendharkar Sameer
• Mathur Guru

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/307

  the doping variations being parallel to the channel lengths · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title