Method of forming a complementary metal-oxide-semiconductor (CMOS) device

Patent metadata

Field	Value
Publication number	US-9349656-B2
Application number	US-201414496225-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	May 7, 2012
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.

First claim

What is claimed is:

1. A method of forming a complementary metal-oxide-semiconductor (CMOS) device, the method comprising:
forming a first layer on an extension layer of a wafer, wherein the extension layer includes a first region associated with a p-type transistor and a second region associated with an n-type transistor, wherein the first region includes a first channel region between a first well implants region and a second well implants region, and wherein the second region includes a second channel region between a third well implants region and a fourth well implants region;
forming a gate on the first region, wherein the gate is in contact with the extension layer and in contact with a first expansion region and a second expansion region that include a portion of the first layer, wherein the first expansion region provides a first conducting path between a first source and the first well implants region, and wherein the second expansion region provides a second conducting path between a first drain and the second well implants region;
forming a second gate on the second region, wherein the second gate is in contact with the extension layer and in contact with a third expansion region and a fourth expansion region formed on a portion of the second region; and
wherein the first expansion region, the second expansion region, the third expansion region, and the fourth expansion region comprise undoped semiconducting material.

2. The method of claim 1 , wherein the first expansion region and the second expansion region comprise silicon germanium.

3. The method of claim 1 , wherein the gate and the second gate are in contact with the first channel region and the second channel region, respectively.

4. The method of claim 1 , wherein the first expansion region and the second expansion region are thicker than the channel region.

5. The method of claim 1 , further comprising forming a layer of a first extension region on a portion of the first layer associated with the first region.

6. The method of claim 5 , wherein the first extension region comprises at least silicon germanium and a material that increases p-type metal-oxide-semiconductor (pMOS) channel mobility.

7. The method of claim 1 , further comprising removing a portion of the first layer, wherein the portion of the first layer is associated with the second region.

8. The method of claim 7 , further comprising forming a layer of a second extension region on a portion of the second region of the extension layer.

9. The method of claim 8 , wherein the second extension region comprises one of silicon and silicon carbon that increases n-type metal-oxide-semiconductor (nMOS) channel mobility.

10. The method of claim 1 , further comprising forming a first dummy gate stack on the first region and forming a second dummy gate stack on the second region.

11. The method of claim 10 , further comprising removing a portion of the first dummy gate stack on the first region to create a first cavity and removing a portion of the second dummy gate stack on the second region to create a second cavity.

12. The method of claim 11 , further comprising removing a portion of the first layer to extend the second cavity to the extension layer.

13. The method of claim 1 , wherein the CMOS device is integrated into one of a set top box, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, and a portable digital video player.

Assignees

• Qualcomm Inc

Inventors

• Yang Bin
• Li Xia
• Yuan Jun

Classifications

• H10D64/01304

  characterised by the conductor · CPC title

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H10D30/751

  having composition variations in the channel regions · CPC title

• H10D64/027

  by etching at gate locations · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title