Three-dimensional microelectronic package with embedded cooling channels

Patent metadata

Field	Value
Publication number	US-10937764-B2
Application number	US-201916351757-A
Country	US
Kind code	B2
Filing date	Mar 13, 2019
Priority date	Mar 13, 2019
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

First claim

What is claimed is:

1. A microelectronic package, comprising:
a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias;
a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second thru-silicon-vias that connect to the first thru-silicon-vias, wherein the silicon cap comprises a first silicon cap and wherein the microelectronic package further comprises:
a second silicon cap bonded to a second surface of a second silicon chip opposite a first surface of the second silicon cap, the second silicon cap enclosing second coolant channels, wherein the first silicon cap and the second silicon cap comprise inlet holes and outlet holes respectively located outside a perimeter of the first silicon chip and the second silicon chip, and wherein the inlet holes and outlet holes respectively connect to manifolds formed within the first silicon chip and the second silicon chip and provide for flowing coolant fluid through the first coolant channels and the second coolant channels: and
the second silicon chip attached to the silicon cap and electrically connected to the second thru-silicon-vias, and wherein the second silicon chip comprises the second coolant channels.

2. The microelectronic package of claim 1 , further comprising:
interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second thru-silicon-vias and electrical components of the second silicon chip.

3. The microelectronic package of claim 1 , further comprising:
a manifold formed within the first silicon chip on opposite sides of the first coolant channels that connects to the first coolant channels.

4. The microelectronic package of claim 3 , further comprising:
inlet holes and outlet holes formed through the silicon cap that respectively connect to the manifold and provide for introducing coolant fluid into the first coolant channels and removing the coolant fluid from the first coolant channels.

5. The microelectronic package of claim 4 , further comprising:
fluid couplings that connect to the inlet holes and the outlet holes via a metal plate formed adjacent to the inlet holes and outlet holes with gaskets formed between the metal plate and the silicon cap.

6. The microelectronic package of claim 1 , further comprising:
a substrate, wherein the first silicon chip is attached to the substrate via a second surface opposite the first surface, and wherein the substrate comprises a material selected from a group consisting of ceramic and one or more laminated dielectric films.

7. The microelectronic package of claim 6 , further comprising:
a stiffener element or a lid attached to a portion of the substrate around the first silicon chip.

8. The microelectronic package of claim 6 , further comprising:
interconnects formed between the substrate and the second surface of the silicon chip; and
redistribution layers located between the first thru-silicon-vias and the interconnects, wherein the redistribution layers respectively connect the second interconnects to the first thru-silicon-vias.

9. The microelectronic package of claim 1 , further comprising:
inlet fluid couplings and outlet fluidic couplings that respectively connect to the inlet and outlet holes via metal plates formed adjacent to the inlet and outlet holes with gaskets respectively formed between the metal plates and respective surfaces of the first silicon cap and the second silicon cap.

10. The microelectronic package of claim 9 , wherein the inlet fluidic couplings are connected to the inlet holes in parallel or in series, and wherein the outlet fluidic couplings are connected to the outlet holes in parallel or in series.

11. The microelectronic package of claim 1 , wherein the second silicon chip further comprises third thru-silicon-vias interspersed between the second coolant channels.

12. The microelectronic package of claim 11 , wherein the second silicon cap further comprises fourth thru-silicon-vias that connect to the third thru-silicon-vias.

13. A microelectronic package, comprising:
silicon chips stacked on and electrically connected to one another, the silicon chips comprising coolant channels interspersed between first thru-silicon-vias, wherein inlet holes and outlet holes respectively located outside a perimeter of the silicon chips, wherein the inlet holes and outlet holes respectively provide for flowing coolant fluid through the coolant channels; and
at least one capping layer formed between adjacent silicon chips of the stacked silicon chips, the capping layer comprising second thru-silicon-vias that connect to the first thru-silicon-vias of the adjacent silicon chips.

14. The microelectronic package of claim 13 , wherein the silicon chips comprise three of more silicon chips.

15. The microelectronic package of claim 13 , further comprising:
inlet hose barbs connected to the inlet holes and outlet hose barbs connected to the outlet holes, wherein the inlet hose barbs are connected to the inlet holes in parallel or in series, and wherein the outlet hose barbs are connected to the outlet holes in parallel or in series.

16. A microelectronic package, comprising:
silicon chips stacked on and electrically connected to one another, wherein the silicon chips comprise coolant channels, and wherein at least one silicon chip of the silicon chips comprises first thru-silicon-vias interspersed between a first set of the coolant channels formed within the at least one silicon chip;
capping layers formed on first surfaces of the silicon chips and enclosing the coolant channels, wherein at least one capping layer of the capping layers comprises second thru-silicon-vias that connect to the first thru-silicon-vias, wherein inlet holes and outlet holes respectively located outside a perimeter of the silicon chips, wherein the inlet holes and outlet holes respectively provide for flowing coolant fluid through the coolant channels.

17. The microelectronic package of claim 16 , wherein the silicon chips comprise three or more silicon chips.

Assignees

• IBM

Inventors

• Sikka Kamal K
• Lie Fee Li
• Winstel Kevin
• Bonam Ravi K
• Saraf Iqbal Rashid
• Goldfarb Dario
• Corliss Daniel
• Gupta Dinesh

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W70/652

  Cross-sectional shapes · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title