Three-dimensional flat NAND memory device having curved memory elements and methods of making the same

Patent metadata

Field	Value
Publication number	US-10930674-B2
Application number	US-202016878865-A
Country	US
Kind code	B2
Filing date	May 20, 2020
Priority date	Feb 18, 2019
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

First claim

What is claimed is:

1. A method of forming a three-dimensional memory device, comprising:
forming alternating stacks of first sacrificial material strips and second sacrificial material strips over a substrate, wherein the alternating stacks are laterally spaced apart from one another by line trenches laterally extending along a first horizontal direction;
modifying the line trenches to provide a two-dimensional array of lateral recesses on each sidewall of the line trenches, wherein each two-dimensional array of lateral recesses is laterally bounded by a respective two-dimensional array of laterally-recessed surfaces of the second sacrificial material strips;
forming memory stack assemblies in each volume that includes a combination of a volume of a line trench and volumes of two adjoining two-dimensional arrays of lateral recesses, wherein each of the memory stack assemblies comprises two two-dimensional arrays of lateral protrusion regions, and each of the lateral protrusion regions comprises a respective charge storage element;
replacing remaining portions of the second sacrificial material strips with electrically conductive strips; and
forming air gap strips by removing the first sacrificial material strips.

2. The method of claim 1 , further comprising:
forming diffusion barrier strips that extend vertically and laterally spaced from one another on each sidewall of the line trenches;
oxidizing surface portions of the second sacrificial material strips at a faster oxidation rate than surfaces portions of the first sacrificial material strips; and
removing the diffusion barrier strips, oxidized portions of the second sacrificial material strips, and oxidized portions of the first sacrificial material strips, wherein the two-dimensional arrays of laterally-recessed surfaces of the second sacrificial material strips are provided.

3. The method of claim 2 , wherein:
the diffusion barrier strips comprise silicon nitride;
the first sacrificial material strips comprise silicon; and
the second sacrificial material strips comprise a silicon-germanium alloy including germanium at a higher atomic concentration than the first sacrificial material strips.

4. The method of claim 3 , further comprising:
forming a diffusion barrier layer on each sidewall of the line trenches;
forming a two-dimensional array of masking material pillars within the line trenches after formation of the diffusion barrier layer; and
isotropically etching physically exposed portions of the diffusion barrier layer that are not masked by the two-dimensional array of masking material pillars, wherein remaining portions of the diffusion barrier layer constitute the diffusion barrier strips.

5. The method of claim 1 , further comprising:
depositing a charge storage material layer over remaining portions of the alternating strips after formation of the two-dimensional arrays of lateral recesses; and
removing portions of the charge storage material layer located outside the two-dimensional arrays of lateral recesses using an anisotropic etch process, wherein remaining portions of the charge storage material layer in the two-dimensional arrays of laterally recesses constitute the charge storage elements.

6. The method of claim 5 , further comprising:
forming a tunneling dielectric layer over each set of charge storage elements located within a respective two-dimensional array of lateral recesses; and
forming a row of vertical semiconductor channels over each tunneling dielectric layer.

7. The method of claim 6 , wherein:
each of the memory stack assemblies comprises two rows of vertical semiconductor channels; and
each vertical semiconductor channel within the two rows of vertical semiconductor channels laterally overlie a respective vertical stack of charge storage elements.

8. The method of claim 7 , further comprising forming a dielectric core in each remaining volume of the line trenches after formation of the vertical semiconductor channels, wherein each dielectric core contacts two rows of vertical semiconductor channels and two tunneling dielectric layers.

Assignees

• Sandisk Technologies Llc

Inventors

• Cui Zhixin
• Nishikawa Masatoshi
• Zhang Yanli

Classifications

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title