Shift register unit for display and driving method thereof, gate driving device

Patent metadata

Field	Value
Publication number	US-10923206-B2
Application number	US-201715760294-A
Country	US
Kind code	B2
Filing date	Sep 19, 2017
Priority date	Feb 6, 2017
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

The embodiments of the present disclosure relate to a shift registers unit and a driving method thereof, and a gate driving device. The shift register unit includes a first and second input circuit, a pull-down control circuit, an output circuit, a pull-down circuit, and a control circuit. The first input circuit provides a first control signal to a pull-up node. The second input circuit provides a second control signal to the pull-up node. The pull-down control circuit provides the voltage of a first voltage terminal to a pull-down node, or controls the voltage of the pull-down node. The output circuit provides a second clock signal to a signal output terminal. The pull-down circuit provides the voltage of the first voltage terminal to the pull-up node and the signal output terminal. The control circuit provides the first input signal to the pull-up node.

First claim

What is claimed is:

1. A shift register unit comprising:
a first input circuit, configured to provide a first control signal from a first signal control terminal to a pull-up node according to a first input signal from a first signal input terminal;
a second input circuit, configured to provide a second control signal from a second signal control terminal to the pull-up node according to a second input signal from a second signal input terminal;
a pull-down control circuit, configured to provide a voltage of a first voltage terminal to a pull-down node according to a voltage of the pull-up node, or to control a voltage of the pull-down node according to a first clock signal from a first clock signal input terminal;
an output circuit, configured to provide a second clock signal from a second clock signal input terminal to a signal output terminal as an output signal according to the voltage of the pull-up node;
a pull-down circuit, configured to provide the voltage of the first voltage terminal to the pull-up node and the signal output terminal according to the voltage of the pull-down node; and
a control circuit, configured to provide the first input signal to the pull-up node according to the first control signal and the first clock signal;
wherein the pull-down control circuit comprises a first transistor, a second transistor, a third transistor, and a first capacitor;
wherein a control electrode and a second electrode of the first transistor are coupled to the first clock signal input terminal, and a first electrode of the first transistor is coupled to the pull-down node;
wherein a control electrode of the second transistor is coupled to the pull-up node, a first electrode of the second transistor is coupled to the first voltage terminal, and a second electrode of the second transistor is coupled to the pull-down node;
wherein a control electrode of the third transistor is coupled to the signal output terminal, a first electrode of the third transistor is coupled to the first voltage terminal, and a second electrode of the third transistor is coupled to the pull-down node; and
wherein the first capacitor is coupled between the pull-down node and the first voltage terminal.

2. The shift register unit according to claim 1 ,
wherein the control circuit comprises a fourth transistor and a fifth transistor;
wherein a control electrode of the fourth transistor is coupled to the first signal control terminal, a first electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, and a second electrode of the fourth transistor is coupled to the first signal input terminal; and
wherein a control electrode of the fifth transistor is coupled to the first clock signal input terminal, a first electrode of the fifth transistor is coupled to the pull-up node, and a second electrode of the fifth transistor is coupled to the first electrode of the fourth transistor.

3. The shift register unit according to claim 1 , wherein the control circuit is further configured to provide the second input signal to the pull-up node according to the second control signal and the first clock signal.

4. The shift register unit according to claim 3 ,
wherein the control circuit comprises a sixth transistor and a seventh transistor;
wherein a control electrode of the sixth transistor is coupled to the second signal control terminal, a first electrode of the sixth transistor is coupled to the second signal input terminal, and a second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor; and
wherein a control electrode of the seventh transistor is coupled to the first clock signal input terminal, a first electrode of the seventh transistor is coupled to the second electrode of the sixth transistor, and a second electrode of the seventh transistor is coupled to the pull-up node.

5. The shift register unit according to claim 1 ,
wherein the first input circuit comprises an eighth transistor; and
wherein a control electrode of the eighth transistor is coupled to the first signal input terminal, a first electrode of the eighth transistor is coupled to the pull-up node, and a second electrode of the eighth transistor is coupled to the first signal control terminal.

6. The shift register unit according to claim 1 ,
wherein the second input circuit comprises a ninth transistor; and
wherein a control electrode of the ninth transistor is coupled to the second signal input terminal, a first electrode of the ninth transistor is coupled to the second signal control terminal, and a second electrode of the ninth transistor is coupled to the pull-up node.

7. The shift register unit according to claim 1 ,
wherein the output circuit comprises a tenth transistor and a second capacitor;
wherein a control electrode of the tenth transistor is coupled to the pull-up node, a first electrode of the tenth transistor is coupled to the signal output terminal, and a second electrode of the tenth transistor is coupled to the second clock signal input terminal; and
wherein the second capacitor is coupled between the pull-up node and the signal output terminal.

8. The shift register unit according to claim 1 ,
wherein the pull-down circuit comprises an eleventh transistor and a twelfth transistor;
wherein a control electrode of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the first voltage terminal, and a second electrode of the eleventh transistor is coupled to the pull-up node; and
wherein a control electrode of the twelfth transistor is coupled to the pull-down node, a first electrode of the twelfth transistor is coupled to the first voltage terminal, and a second electrode of the twelfth transistor is coupled to the signal output terminal.

9. A method for driving a shift register unit, the method comprising:
turning on a first input circuit according to a first input signal from a first signal input terminal to provide a first control signal from a first signal control terminal to a pull-up node, turning on a control circuit according to the first control signal and a first clock signal from a first clock signal input terminal to provide the first input signal to the pull-up node, and turning on an output circuit according to the voltage of the pull-up node to output a second clock signal from a second clock signal input terminal to a signal output terminal;
maintaining the voltage of the pull-up node to keep the output circuit turned on to output the second clock signal to the signal output terminal, and controlling the voltage of a pull-down node by a pull-down control circuit according to the voltage of the pull-up node;
turning on a second input circuit according to a second input signal from a second signal input terminal to provide a second control signal from a second signal control terminal to the pull-up node to turn off the output circuit, and providing the first clock signal to the pull-down node according to the first clock signal to turn on a pull-down circuit to provide the voltage of a first voltage terminal to the pull-up node and the signal output terminal;
turning on a second input circuit according to the second input signal to provide the second control signal to the pull-up node, turning on the control circuit according to the second control signal and the first clock signal to provide the first input signal to the pull-up node, and turning on the output circuit according to the voltage of the pull-up node to output the second clock signal to the signal output terminal;
maintaining the voltage of the pull-up node to keep the output circuit turned on to output the second clock signal to the signal o

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Wang Zhen
• Sun Jian
• Qiao Yun
• Zhan Xiaozhou
• Huang Fei
• Zhang Han
• Qin Wenwen
• Cong Lele
• Wang Zhengkui

Classifications

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title