Shift register unit, gate driving circuit and driving method thereof, and array substrate

Patent metadata

Field	Value
Publication number	US-2016358666-A1
Application number	US-201615133398-A
Country	US
Kind code	A1
Filing date	Apr 20, 2016
Priority date	Jun 8, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A shift register unit is provided. The shift register unit includes a first input module configured to output a first voltage signal as a pull-up control signal under the control of a first signal, a first reset module configured to reset the pull-up control signal under the control of a first reset signal, a pull-up module configured to output a first clock signal under the control of the pull-up control signal, a pull-down control module configured to output a second clock signal as a pull-down control signal under the control of a second clock signal, a pull-down module configured to pull down a voltage of the pull-up control signal, a first output module, and a second output module.

First claim

1 . A shift register unit comprising:
a first input module connected to a first voltage terminal to receive a first voltage signal, and connected to a first signal input terminal to receive a first signal, the first input module configured to output the first voltage signal as a pull-up control signal under the control of the first signal; a first reset module connected to the first input module, connected to a second voltage terminal to receive a second voltage signal, and connected to a first reset signal terminal to receive a first reset signal, the first reset module configured to reset the pull-up control signal under the control of the first reset signal; a pull-up module connected to the first input module, and connected to a first clock signal terminal to receive a first clock signal, the pull-up module configured to output the first clock signal under the control of the pull-up control signal, wherein the first clock signal is output as a third output signal via a third signal output terminal; a pull-down control module connected to the first input module, connected to a second clock signal terminal to receive a second clock signal, and connected to a third voltage terminal to receive a third voltage signal, the pull-down control module configured to output the second clock signal as a pull-down control signal under the control of the second clock signal, and configured to pull down a voltage of the pull-down control signal to be equal to the third voltage signal under the control of the pull-up control signal; a pull-down module connected to the first input module, the pull-down control module, and the pull-up module, and further connected to the third voltage terminal to receive the third voltage signal, the pull-down configured to pull down a voltage of the pull-up control signal and a voltage of the third output signal to be equal to the third voltage signal under the control of the pull-down control signal; a first output module connected to a third clock signal terminal to receive a third clock signal, and connected to the pull-up module, the first output module configured to output the third clock signal, under the control of the third output signal, as a first output signal via a first signal output terminal; and a second output module connected to a fourth clock signal terminal to receive a fourth clock signal, and connected to the pull-up module, the second output module configured to output the fourth clock signal, under the control of the third output signal, as a second output signal via a second signal output terminal.

2 . The shift register unit according to claim 1 , further comprising a second input module connected to the first voltage terminal to receive the first voltage signal, and connected to a second signal input terminal to receive the second signal, the second input module configured to output the first voltage signal as the pull-up control signal under the control of the second signal.

3 . The shift register unit according to claim 2 , further comprising a second reset module connected to the second voltage terminal to receive the second voltage signal, and connected to a second reset signal terminal to receive a second reset signal, the second reset module configured to reset the pull-up control signal under the control of the second reset signal.

4 . The shift register unit according to claim 1 , wherein the first output module comprises a twelfth transistor, wherein a gate of the twelfth transistor is connected to the pull-up module, a first electrode of the twelfth transistor is connected to the first signal output terminal, and a second electrode of the twelfth transistor is connected to the third clock signal terminal.

5 . The shift register unit according to claim 1 , wherein the second output module comprises a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the pull-up module, a first electrode of the thirteenth transistor is connected to the fourth clock signal terminal, and a second electrode of the thirteenth transistor is connected to the second signal output terminal.

6 . The shift register unit according to claim 2 , wherein the second input module comprises a fourteenth transistor, wherein a gate of the fourteenth transistor is connected to the second signal input terminal, a first electrode of the fourteenth transistor is connected to the pull-up module, and a second electrode of the fourteenth transistor is connected to the first voltage terminal.

7 . The shift register unit according to claim 3 , wherein the second reset module comprises a fifteenth transistor, wherein a gate of the fifteenth transistor is connected to the second reset signal terminal, a first electrode of the fifteenth transistor is connected to the second voltage terminal, and a second electrode of the fifteenth transistor is connected to the second input module.

8 . The shift register unit according to claim 1 , wherein the first input module comprises a first transistor, wherein a gate of the first transistor is connected to the first signal input terminal, a first electrode of the first transistor is connected to the pull-up module, and a second electrode of the first transistor is connected to the first voltage terminal.

9 . The shift register unit according to claim 1 , wherein the first reset module comprises a second transistor, wherein a gate of the second transistor is connected to the first reset signal terminal, a first electrode of the second transistor is connected to the second voltage terminal, and a second electrode of the second transistor is connected to the first input module.

10 . The shift register unit according to claim 1 , wherein the pull-up module comprises:
a third transistor, wherein a gate of the third transistor is connected to the first input module, a first electrode of the third transistor is connected to the third signal output terminal, and a second electrode of the third transistor is connected to the first clock signal terminal; and a storage capacitor connected between the gate of the third transistor and the first electrode of the third transistor.

11 . The shift register unit according to claim 3 , wherein the pull-up module comprises:
a third transistor, wherein a gate of the third transistor is connected to the first input module and the second input module, a first electrode of the third transistor is connected to the third signal output terminal, and a second electrode of the third transistor is connected to the first clock signal terminal; and a storage capacitor connected between the gate of the third transistor and the first electrode of the third transistor.

12 . The shift register unit according to claim 1 , wherein the pull-down module comprises a fifth transistor, a sixth transistor, an eighth transistor, and a ninth transistor,
wherein a gate of the fifth transistor is connected to a second electrode of the eighth transistor, a first electrode of the fifth transistor is connected to the pull-down module, and a second electrode of the fifth transistor is connected to the second clock signal terminal, wherein a gate of the sixth transistor is connected to the first input module, a first electrode of the sixth transistor is connected to the third voltage terminal, and a second electrode of the sixth transistor is connected to the first electrode of the fifth transistor, wherein a gate of the eighth transistor is connected to the pull-up module, and a first electrode of the eighth transistor is connected to the third voltage terminal, and wherein a gate and second electrode of the ninth transistor are each connected to the second clock signal terminal, and a firs

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Pang Fengchun

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title