Shift register unit and driving method thereof, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-2016358566-A1
Application number	US-201515031174-A
Country	US
Kind code	A1
Filing date	Nov 10, 2015
Priority date	Jun 8, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

A shift register unit and a driving method thereof, a gate driving circuit and a display device. In the shift register unit, an input module outputs a pull-up control signal to a pull-up module based on a first DC voltage signal and a start signal, the pull-up module outputs a shift signal via a first output port and output a start signal for a next stage of shift register unit via a second output port, a pull-down control module outputs a pull-down control signal to a pull-down module, the pull-down module outputs to the pull-up module a pull-down signal for the first output port, the second output port and a pull-up point, a reset module resets the pull-up module. DC voltages are used as input signals of the pull-up module and the pull-down control module, which is stable and has a small power consumption.

First claim

1 . A shift register unit comprising an input module, a pull-down control module, a pull-down module, a pull-up module and a reset module,
wherein the input module is connected with the pull-up module, and configured to output a pull-up control signal to the pull-up module based on a first DC voltage signal and a start signal, wherein the pull-up module is configured to output a shift signal via a first output port and output a start signal for a next stage of shift register unit via a second output port, based on a second DC voltage signal and a clock signal, wherein the pull-down control module is connected with the pull-down module and the pull-up module, and configured to output a pull-down control signal to the pull-down module based on the second DC voltage signal, a third DC voltage signal and the clock signal, wherein the pull-down module is connected with the pull-up module, and configured to output to the pull-up module a pull-down signal for the first output port, the second output port and a pull-up point, and wherein the reset module is connected with the pull-up module, and configured to reset the pull-up module based on a fourth DC voltage signal and a reset signal.

2 . The shift register unit according to claim 1 , wherein the input module includes a first transistor, wherein a control electrode of the first transistor is connected with an input port of the start signal, a first electrode of the first transistor is connected with an input port of the first DC voltage signal, and a connection point connecting a second electrode of the first transistor and the pull-up module forms the pull-up point.

3 . The shift register unit according to claim 2 , wherein the pull-up module includes a third transistor, an eighth transistor and a first capacitor,
wherein a control electrode of the third transistor is connected with the second electrode of the first transistor, a first electrode of the third transistor is connected with an input port of the second DC voltage signal, and a second electrode of the third transistor is connected with the pull-down module, and wherein the second electrode forms the first output port, wherein a control electrode of the eighth transistor is connected with the second electrode of the first transistor, a first electrode of the eighth transistor is connected with an input port of the clock signal, and a second electrode of the eighth transistor is connected with a second port of the first capacitor, and wherein a connection point connecting the second electrode of the eighth transistor and the second port of the first capacitor forms the second output port, wherein a first port of the capacitor is connected with the second electrode of the first transistor, and wherein a connection point connecting the second electrode of the first transistor, the control electrode of the third transistor, the control electrode of the eighth transistor and the first port of the first capacitor forms the pull-up point.

4 . The shift register unit according to claim 3 , wherein the pull-down control module includes a fourth transistor, a fifth transistor, a sixth transistor and a ninth transistor,
wherein a control electrode of the fourth transistor is connected with the input port of the clock signal, a first electrode of the fourth transistor is connected with a control electrode of the sixth transistor, and a second electrode of the fourth transistor is connected with an input port of the third DC voltage signal, wherein a control electrode and a first electrode of the fifth transistor are each connected with the input port of the second DC voltage signal, and a second electrode of the fifth transistor is connected with the control electrode of the sixth transistor, wherein a first electrode of the sixth transistor is connected with the input port of the second DC voltage signal, and a second electrode of the sixth transistor is connected with the pull-down module, and wherein a control electrode of the ninth transistor is connected with the second electrode of the first transistor, a first electrode of the ninth transistor is connected with the pull-down module, and a second electrode of the ninth transistor is connected with the input port of the third DC voltage signal.

5 . The shift register unit according to claim 4 , wherein the pull-down module includes a seventh transistor, a tenth transistor, and an eleventh transistor,
wherein a control electrode of the seventh transistor is connected with the second electrode of the sixth transistor, a first electrode of the seventh transistor is connected with the second port of the first capacitor, and a second electrode of the seventh transistor is connected with the input port of the third DC voltage signal, wherein a control electrode of the tenth transistor is connected with the second electrode of the sixth transistor, a first electrode of the tenth transistor is connected with the control electrode of the third transistor, and a second electrode of the tenth transistor is connected with the input port of the third DC voltage signal, wherein a control electrode of the eleventh transistor is connected with the second electrode of the sixth transistor, a first electrode of the eleventh transistor is connected with the second electrode of the third transistor, and a second electrode of the eleventh transistor is connected with the input port of the third DC voltage signal, and wherein, a connection point connecting the control electrode of the seventh transistor, the first electrode of the ninth transistor, the second electrode of the sixth transistor, the control electrode of the tenth transistor and the control electrode of the eleventh transistor forms a pull-down point.

6 . The shift register unit according to claim 5 , wherein the reset module includes a second transistor, wherein a control electrode of the second transistor is connected with an input port of the reset signal, a first electrode of the second transistor is connected with the control electrode of the third transistor, and a second electrode of the second transistor is connected with an input port of the fourth DC voltage signal.

7 . The shift register unit according to claim 6 , wherein all the transistors from the first transistor to the eleventh transistor are N-type transistors, or
wherein all the transistors from the first transistor to the eleventh transistor are P-type transistors, or wherein a part of the transistors from the first transistor to the eleventh transistor are P-type transistors, and the others are N-type transistors.

8 . A gate driving circuit comprising a plurality of shift register units according to claim 1 , wherein the plurality of shift register units are connected in cascade, an input module of the shift register unit is inputted with an output signal outputted by the second output port of a previous stage of shift register unit, a reset module of the shift register unit is provided with an output signal outputted by the second output port of a next stage of shift register unit.

9 . A display device comprising a gate driving circuit according to claim 8 .

10 . A driving method for driving a shift register unit according to claim 1 , comprising:
a pre-output phase: providing an effective start signal, wherein the pull-up point is charged, and a voltage of the pull-down point is at low level, the first output port outputs a shift signal of which a voltage rises gradually, and a voltage of the second output port is at low level, an output phase: providing an effective clock signal, wherein the charging of pull-up point is completed and a voltage of the pull-up point is at high level, the voltage of the pull-down point is maintained at l

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Li Jinyu
• Cao Xue

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title