Semiconductor layered device with data bus inversion

Patent metadata

Field	Value
Publication number	US-10922262-B2
Application number	US-202016840281-A
Country	US
Kind code	B2
Filing date	Apr 3, 2020
Priority date	May 23, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

First claim

What is claimed is:

1. An apparatus, comprising:
a first plurality of first-in first-out (FIFO) circuits configured to receive at least a first portion of a plurality of corresponding bits of data, and further configured to provide a plurality of corresponding bits of first latched data;
a second plurality of FIFO circuits configured to receive at least a second portion of the plurality of corresponding bits of data, and further configured to provide a plurality of corresponding bits of second latched data; and
a DBI calculator configured to receive the plurality of corresponding bits of the first latched data and the plurality of corresponding bits of the second latched data and further configured to provide a current DBI calculation result signal after a data bus inversion (DBI) calculation time,
wherein the first plurality of FIFO circuits and the second plurality of FIFO circuits are configured to hold the plurality of corresponding bits of first latched data and corresponding bits of second latched data, respectively for the DBI calculation time, before providing the plurality of corresponding bits of first latched data and corresponding bits of second latched data, respectively.

2. The apparatus of claim 1 wherein the first plurality of FIFO circuits and the second plurality of FIFO circuits are alternately activated by respective pointer signals to receive the first and second portions of the plurality of corresponding bits of data, respectively.

3. The apparatus of claim 1 wherein the first plurality of FIFO circuits are configured to provide the plurality of corresponding bits of the first latched data inverted or not based on the DBI calculation result signal.

4. The apparatus of claim 1 , further comprising a second DBI calculator configured to receive the plurality of corresponding bits of the first latched data and the plurality of corresponding bits of the second latched data and further configured to provide a second current DBI calculation result signal after the DBI calculation time to the second plurality of FIFO circuits.

5. The apparatus of claim 4 wherein the first and second plurality of FIFO circuits are alternately activated by respective pointer signals to receive the first and second portions of the plurality of corresponding bits of data, respectively, and wherein the DBI calculator and the second DBI calculator are alternately activated by the respective first and second pointer signals to receive the to receive the plurality of corresponding bits of the first latched data and the plurality of corresponding bits of the second latched data.

6. The apparatus of claim 1 wherein the DBI calculator is configured to provide the current DBI calculation result signal to the first plurality of FIFO circuits before the first plurality of FIFO circuits provides the plurality of corresponding bits of first latched data.

7. The apparatus of claim 1 wherein the first plurality of FIFO circuits comprise a plurality of series-coupled flip-flop circuits, wherein the plurality of series-coupled flip-flop circuits are alternately activated to latch bits of the plurality of corresponding bits of data.

8. The apparatus of claim 7 wherein a first flip-flop circuit and a third flip-flop circuit of the plurality of series-coupled flip-flop circuits are activated concurrently, and a second flip-flop circuit of the plurality of series-coupled flip-flop circuits is alternately activated with the first and third flip-flop circuits of the plurality of series-coupled flip-flop circuits.

9. The apparatus of claim 1 wherein the DBI calculator comprises a first plurality of flip-flop circuits and a second plurality of flip-flop circuits, wherein the first plurality of flip-flop circuits and second plurality of flip-flop circuits are alternately activated to latch signals responsive to a pointer signal.

10. The apparatus of claim 1 , further comprising a plurality of flip-flop circuits configured to receive the plurality of corresponding bits of second latched data and configured to provide the plurality of corresponding bits of the second latched data to the DBI calculator at a time concurrent with the DBI calculator receiving the plurality of corresponding bits of the first latched data.

11. An apparatus, comprising:
first and second pluralities of first-in first-out (FIFO) circuits configured to alternately receiving a first plurality of bits of data with receiving a second plurality of bits of data and further configured to alternately providing a first plurality of bits of latched data with providing a second plurality of bits of latched data, all respectively; and
a DBI calculator configured to calculate a current data bus inversion (DBI) calculation result signal after a DBI calculation time based on the first plurality of bits of latched data and the second plurality of bits of latched data,
wherein the first plurality of bits of latched data based on the received first plurality of bits of data and the second plurality of bits of latched data based on the received second plurality of bits of data, and
wherein the first plurality of bits of latched data are held for the DBI calculation time before providing the first plurality of bits of latched data.

12. The apparatus of claim 11 wherein each of the first plurality of FIFO circuits comprises:
a plurality of series-coupled flip-flop circuits configured to alternately latch the first plurality of bits of data; and
a plurality of bit inverters configured to receive respective bits from the plurality of series-coupled flip-flop circuits and invert the received respective bits based on the current DBI calculation result signal.

13. The apparatus of claim 11 , further comprising a second DBI calculator configured to calculate a second current DBI calculation result signal after the DBI calculation time based on the second plurality of bits of latched data and a third plurality of bits of latched data provided by the first plurality of FIFO circuits, wherein the DBI calculator and the second DBI calculator are configured to alternately provide the current DBI calculation result signal and the second current DBI calculation result signal.

14. The apparatus of claim 11 , further comprising a plurality of output circuits configured to receive the first plurality of bits of latched data and the second plurality of bits of latched data, and further configured to provide data output signals.

15. The apparatus of claim 11 wherein the DBI calculator comprises:
a plurality of comparators configured to receive the first plurality of bits of latched data and the second plurality of bits of latched data and further configured to provide result signals indicative of comparisons between corresponding bits of the first plurality of bits of latched data and the second plurality of bits of latched data;
a first plurality of flip-flop circuits configured to receive the result signals from the plurality of comparators; and
a second plurality of flip-flop circuits configured to receive output signals of the first plurality of flip-flop circuits,
wherein the first plurality of flip-flop circuits and second plurality of flip-flop circuits are alternately activated to latch signals responsive to a pointer signal.

16. A method, comprising:
alternately receiving a first plurality of bits of data with receiving a second plurality of bits of data;
alternately providing a first plurality of bits of latched data with providing a second plurality of bits of latched data, the first plurality of bits of latched data based on the received first plurality of bits of data

Assignees

• Micron Technology Inc

Inventors

• Ebihara Yuki
• Narui Seiji

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F13/4265 Primary

  on a point to point bus (G06F13/4247, G06F13/4282 take precedence) · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4023

  using field effect transistors · CPC title