Semiconductor memory apparatus and system including the same

Patent metadata

Field	Value
Publication number	US-2016141010-A1
Application number	US-201514638418-A
Country	US
Kind code	A1
Filing date	Mar 4, 2015
Priority date	Nov 17, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A semiconductor memory apparatus includes a DBI calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block. The DBI calculation block performs a DBI calculation and outputs a DBI result signal based on a result of the DBI calculation. The inversion latch block inverts data and outputs the inverted data when a DBI enable signal is enabled. The inverted data selective output block outputs the inverted data as a data inversion signal in response to the DBI result signal and a pipe input signal. The pipe latch block receives the data, which is not inverted, and the inverted data, and outputs one of the data and the inverted data according to the result of the DBI calculation.

First claim

What is claimed is:

1 . A semiconductor memory apparatus comprising:
a DBI calculation block configured to perform a DBI calculation and output a DBI result signal based on a result of the DBI calculation; an inversion latch block configured to invert data and output the inverted data when a DBI enable signal is enabled; an inverted data selective output block configured to output the to inverted data as a data inversion signal in response to the DBI result signal and a pipe input signal; and a pipe latch block configured to receive the data, which is not inverted, and the inverted data, and output one of the data and the inverted data according to the result of the DBI calculation.

2 . The semiconductor memory apparatus according to claim 1 , wherein the inversion latch block inverts the data and outputs inverted data when the pipe input signal and the DBI enable signal are enabled.

3 . The semiconductor memory apparatus according to claim 2 , wherein the inversion latch block comprises:
a data inversion unit configured to invert the data when the DBI enable signal is enabled; a latch clock generation unit configured to generate a latch clock which is enabled when the pipe input signal is enabled; and a data storage unit configured to receive and store an output signal of the data inversion unit and output the stored signal as the inverted data when the latch clock is enabled.

4 . The semiconductor memory apparatus according to claim 1 , wherein the inverted data selective output block outputs the inverted data as the data inversion signal in response to the DBI result signal when the DBI enable signal is enabled and the pipe input signal is disabled.

5 . The semiconductor memory apparatus according to claim 4 , wherein the inverted data selective output block comprises:
a switch control unit configured to generate a switch enable signal in response to the DBI result signal when the DBI enable signal is enabled and the pipe input signal is disabled; and a switch configured to output the inverted data as the data inversion signal when the switch enable signal is enabled.

6 . The semiconductor memory apparatus according to claim 1 , wherein the pipe latch block receives and stores the data when the pipe input signal is enabled, inverts the stored data or retains the stored data in response to the data inversion signal, and outputs the inverted or retained data when a pipe output signal is enabled.

7 . The semiconductor memory apparatus according to claim 6 , wherein the pipe latch block comprises:
a switch configured to receive the data when the pipe input signal is enabled; a latch unit configured to store an output signal of the switch, and invert or retain the stored data in response to the data inversion signal; and a driver configured to amplify and output an output signal of the latch unit in response to the pipe output signal.

8 . A semiconductor memory apparatus comprising:
a DBI calculation block configured to perform a DBI calculation and output a DBI result signal based on a result of the DBI calculation; is an inversion latch block configured to invert data and output the inverted data in response to a first pipe input signal, a second pipe input signal and a DBI enable signal; an inverted data selective output block configured to output the inverted data as one of a first data inversion signal and a second data inversion signal in response to the DBI result signal, a first pipe input pulse, a second pipe input pulse and the DBI enable signal; a first pipe latch block configured to receive and store the data in response to the first pipe input signal, invert or retain the stored data in response to the first data inversion signal, and output the inverted or retained data in response to a first pipe output signal; and a second pipe latch block configured to receive and store the data in response to the second pipe input signal, invert or retain the stored data in response to the second data inversion signal, and output the inverted or retained data in response to a second pipe output signal.

9 . The semiconductor memory apparatus according to claim 8 , further comprising:
a pulse generation block configured to generate the first pipe input pulse which is enabled when the first pipe input signal is disabled, and generate the second pipe input pulse which is enabled when the second pipe input signal is disabled.

10 . The semiconductor memory apparatus according to claim 8 , wherein the DBI calculation block performs the DBI calculation in response to the data when the DBI enable signal is enabled.

11 . The semiconductor memory apparatus according to claim 8 , wherein the inversion latch block inverts the data and outputs inverted data when one of the first pipe input signal and the second pipe input signal is enabled while the DBI enable signal is enabled.

12 . The semiconductor memory apparatus according to claim 11 wherein the inversion latch block comprises:
a data inversion unit configured to invert the data when the DBI enable signal is enabled;
a latch clock generation unit configured to generate a latch clock which is enabled when one of the first and second pipe input signals is enabled; and
a data storage unit configured to receive and store an output signal of the data inversion unit and output the stored signal as the inverted data when the latch clock is enabled.

13 . The semiconductor memory apparatus according to claim 9 ,
wherein the inverted data selective output block outputs the inverted data as the first data inversion signal in response to the DBI result signal when the DBI enable signal and the first pipe input pulse are enabled, and wherein the inverted data selective output block outputs the inverted data as the second data inversion signal in response to the DBI result signal when the DBI enable signal and the second pipe input pulse are enabled.

14 . The semiconductor memory apparatus according to claim 13 , wherein the inverted data selective output block comprises:
a switch control unit configured to generate a first switch enable signal in response to the DBI result signal when the DBI enable signal and the first pipe input pulse are enabled, and generate a second switch enable signal in response to the DBI result signal when the DBI enable signal and the second pipe input pulse are enabled; a first switch configured to output the inverted data as the first data inversion signal when the first switch enable signal is enabled; and a second switch configured to output the inverted data as the second data inversion signal when the second switch enable signal is enabled.

15 . The semiconductor memory apparatus according to claim 8 , wherein each of the first and second pipe latch blocks comprises:
a switch configured to receive the data when each of the first and second pipe input signals is enabled; a latch unit configured to store an output signal of the switch, and invert or retain the stored data in response to each of the first and second data inversion signals; and a driver configured to amplify and output an output signal of the latch unit in response to each of the first and second pipe output signals.

Assignees

• Sk Hynix Inc

Inventors

• Yun Dae Ho

Classifications

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title