Apparatus including tsv structure
US-2024421040-A1 · Dec 19, 2024 · US
This page is not indexed by search engines while we improve data quality.
Narui Seiji patents
Narui Seiji is listed as an inventor on 48 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Narui Seiji |
| Total patents | 48 |
| First publication | Feb 3, 2015 |
| Latest publication | Dec 19, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatuses, systems, and methods for counter-based read clock in stacked memory devices
US-11869580-B2 · Jan 9, 2024 · US
Apparatuses, systems, and methods for read clock timing alignment in stacked memory devices
US-11854601-B2 · Dec 26, 2023 · US
Semiconductor device with first-in-first-out circuit
US-11805638-B2 · Oct 31, 2023 · US
Methods and apparatuses for aligning read data in a stacked semiconductor device
US-11763855-B2 · Sep 19, 2023 · US
Apparatuses, systems, and methods for counter-based read clock in stacked memory devices
US-2023215494-A1 · Jul 6, 2023 · US
Layouts of data pads on a semiconductor die
US-2023215828-A1 · Jul 6, 2023 · US
Apparatuses, systems, and methods for read clock timing alignment in stacked memory devices
US-2023206985-A1 · Jun 29, 2023 · US
Apparatuses and methods for semiconductor devices including clock signal lines
US-11264068-B2 · Mar 1, 2022 · US
Memory core chip having TSVs
US-11244888-B2 · Feb 8, 2022 · US
Recent patents
Latest publications not already listed above.
Methods and apparatuses for aligning read data in a stacked semiconductor device
US-2021264955-A1 · Aug 26, 2021 · US
Semiconductor device with first-in-first-out circuit
US-2021225848-A1 · Jul 22, 2021 · US
Memory Core Chip Having TSVS
US-2021183744-A1 · Jun 17, 2021 · US
Methods and apparatuses for aligning read data in a stacked semiconductor device
US-11004475-B2 · May 11, 2021 · US
Apparatuses and methods for semiconductor devices including clock signal lines
US-2021104269-A1 · Apr 8, 2021 · US
Semiconductor device with first-in-first-out circuit
US-10964702-B2 · Mar 30, 2021 · US
High bandwidth memory having plural channels
US-10943622-B2 · Mar 9, 2021 · US
Memory device with write data bus control
US-10943625-B2 · Mar 9, 2021 · US
Semiconductor layered device with data bus inversion
US-10922262-B2 · Feb 16, 2021 · US
Memory core chip having TSVS
US-10916489-B1 · Feb 9, 2021 · US
Apparatuses and methods for semiconductor devices including clock signal lines
US-10885959-B1 · Jan 5, 2021 · US
High Bandwidth Memory Having Plural Channels
US-2020411062-A1 · Dec 31, 2020 · US
High bandwidth memory having plural channels
US-10777232-B2 · Sep 15, 2020 · US
High bandwidth memory having plural channels
US-2020251148-A1 · Aug 6, 2020 · US
Semiconductor layered device with data bus inversion
US-2020233828-A1 · Jul 23, 2020 · US
Semiconductor layered device with data bus inversion
US-10664432-B2 · May 26, 2020 · US
Memory device with write data bus control
US-2020126603-A1 · Apr 23, 2020 · US
Semiconductor device with first-in-first-out circuit
US-2020126993-A1 · Apr 23, 2020 · US
Memory device with write data bus control
US-10553263-B2 · Feb 4, 2020 · US
Semiconductor layered device with data bus inversion
US-2019361835-A1 · Nov 28, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 40 |
| Ps4 Luxco Sarl | 8 |
| Elpida Memory Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/00 | 20 |
| G11C7/222 | 20 |
| G11C11/4093 | 18 |
| G11C5/025 | 17 |
| G11C5/04 | 17 |