Semiconductor device

Patent metadata

Field	Value
Publication number	US-10916534-B2
Application number	US-201916395691-A
Country	US
Kind code	B2
Filing date	Apr 26, 2019
Priority date	Jul 19, 2018
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a first fin pattern and a second fin pattern in a NMOS region of the substrate, each extending lengthwise along a first direction and separated by a first trench, and a third fin pattern and a fourth fin pattern in a PMOS region of the substrate, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench;
a first isolation layer in the first trench;
a second isolation layer in the second trench;
a first gate electrode extending lengthwise along a second direction transverse to the first direction and crossing the first fin pattern;
a second gate electrode extending lengthwise along the second direction and crossing the second fin pattern;
a third gate electrode extending lengthwise along the second direction on the second isolation layer; and
a fourth gate electrode extending lengthwise along the second direction on the second isolation layer and spaced apart from the third gate electrode.

2. The semiconductor device of claim 1 , wherein the third gate electrode and the fourth gate electrode are not disposed on upper surfaces of the third fin pattern and the fourth fin pattern.

3. The semiconductor device of claim 1 , further comprising:
a first gate spacer on a sidewall of the third gate electrode and in contact with the third fin pattern; and
a second gate spacer on a sidewall of the fourth gate electrode and in contact with the fourth fin pattern.

4. The semiconductor device of claim 3 , wherein at least a part of the first gate spacer is disposed on an upper surface of the third fin pattern, and wherein at least a part of the second gate spacer is disposed on an upper surface of the fourth fin pattern.

5. The semiconductor device of claim 1 , further comprising:
a first gate spacer on a sidewall of the first gate electrode and not overlapping the first isolation layer; and
a second gate spacer on a sidewall of the second gate electrode and not overlapping the first isolation layer.

6. The semiconductor device of claim 1 , wherein an upper surface of the first isolation layer is higher than upper surfaces of the first fin pattern and the second fin pattern, and wherein an upper surface of the second isolation layer is lower than upper surfaces of the third fin pattern and the fourth fin pattern.

7. The semiconductor device of claim 6 , wherein the upper surface of the first isolation layer is higher than or at the same level as an upper surface of the first gate electrode.

8. The semiconductor device of claim 1 , wherein an upper surface of the first isolation layer is lower than upper surfaces of the first fin pattern and the second fin pattern, and wherein an upper surface of the second isolation layer is lower than upper surfaces of the third fin pattern and the fourth fin pattern.

9. The semiconductor device of claim 1 , wherein a width of the first trench is less than a width of the second trench.

10. The semiconductor device of claim 1 , wherein the first gate electrode is directly connected to the third gate electrode, and wherein the second gate electrode is directly connected to the fourth gate electrode.

11. A semiconductor device comprising:
a substrate comprising a first fin pattern and a second fin pattern in a NMOS region of the substrate, each extending lengthwise along a first direction and separated by a first trench having a first width and a third fin pattern and a fourth fin pattern in a PMOS region of the substrate, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench having a second width greater than the first width;
a first gate electrode crossing the first fin pattern;
a second gate electrode crossing the second fin pattern and spaced apart from the first gate electrode by a first distance greater than or equal to the first width; and
a third gate electrode and a fourth gate electrode between the third fin pattern and the fourth fin pattern.

12. The semiconductor device of claim 11 , wherein the third gate electrode wraps around an end of the third fin pattern and wherein the fourth gate electrode wraps around an end of the fourth fin pattern.

13. The semiconductor device of claim 11 , further comprising:
a first gate spacer on a sidewall of the first gate electrode; and
a second gate spacer on a sidewall of the second gate electrode,
wherein the first and second gate spacers are separated by a distance equal to the first width.

14. The semiconductor device of claim 13 , further comprising an isolation layer in the first trench and between the first and second spacers.

15. The semiconductor device of claim 11 , further comprising:
a first isolation layer in the first trench; and
a second isolation layer in the second trench.

16. A semiconductor device comprising:
a substrate comprising a first fin pattern and a second fin pattern in a NMOS region of the substrate, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region of the substrate, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench;
a first isolation layer in the first trench;
a second isolation layer in the second trench;
a first gate electrode extending lengthwise along a second direction transverse to the first direction and crossing the first fin pattern; and
a second gate electrode extending lengthwise along the second direction and crossing the second fin pattern,
wherein the first gate electrode and the second gate electrode are disposed between the third fin pattern and the fourth fin pattern and do not overlap the first trench.

17. The semiconductor device of claim 16 , wherein each of the first gate electrode and the second gate electrode do not cross the third fin pattern and the fourth fin pattern.

18. The semiconductor device of claim 16 , wherein an upper surface of the first isolation layer is lower than upper surfaces of the first fin pattern and the second fin pattern.

19. The semiconductor device of claim 16 , wherein an upper surface of the first isolation layer is higher than an upper surface of the first gate electrode.

20. The semiconductor device of claim 19 , wherein the first isolation layer extends between the third fin pattern and the fourth fin pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ha Seung Seok
• Park Kyoung-Mi
• Song Hyun-Seung
• Cheon Keon Yong
• Ha Dae Won

Classifications

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title