Semiconductor device packages and stacked package assemblies including high density interconnections

Patent metadata

Field	Value
Publication number	US-10916429-B2
Application number	US-201916705018-A
Country	US
Kind code	B2
Filing date	Dec 5, 2019
Priority date	Aug 11, 2016
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.

First claim

What is claimed is:

1. A semiconductor device package comprising:
a redistribution stack including
a dielectric layer defining a first opening; and
a redistribution layer (RDL) disposed over the dielectric layer and including a first trace,
wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace,
wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.

2. The semiconductor device package of claim 1 , wherein the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace.

3. The semiconductor device package of claim 2 , wherein the maximum width of the second portion of the first trace is substantially the same as the width of the first portion of the first trace.

4. The semiconductor device package of claim 1 , wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

5. The semiconductor device package of claim 1 , further comprising an electronic device including an active surface and a contact pad adjacent to the active surface, wherein the first opening exposes at least a portion of the contact pad, the second portion of the first trace extends between the first portion of the first trace and the exposed portion of the contact pad.

6. The semiconductor device package of claim 5 , wherein a projection area of the first trace onto the contact pad is no greater than 15% of a total area of the contact pad.

7. The semiconductor device package of claim 5 , wherein the RDL further includes at least two additional traces extending over the dielectric layer and overlapping the contact pad disposed below the additional traces.

8. The semiconductor device package of claim 5 , further comprising a package body encapsulating portions of the electronic device, wherein the package body includes a front surface and a back surface opposite to the front surface, the active surface of the electronic device is at least partially exposed from the front surface of the package body, and the redistribution stack is disposed over the front surface of the package body.

9. The semiconductor device package of claim 8 , wherein the electronic device is a first electronic device, the semiconductor device package further comprises a second electronic device, wherein the package body encapsulates portions of the second electronic device, and the RDL electrically connects the first electronic device to the second electronic device.

10. The semiconductor device package of claim 8 , further comprising an interposer component including a lower surface, an upper surface, and a conductive via extending from the lower surface to the upper surface, wherein the package body encapsulates portions of the interposer component, the lower surface of the interposer component is at least partially exposed from the front surface of the package body, the upper surface of the interposer component is at least partially exposed from the back surface of the package body, and the RDL electrically connects the electronic device to the interposer component.

11. The semiconductor device package of claim 10 , wherein the dielectric layer defines a second opening exposing at least a portion of the conductive via, the RDL includes a second trace, the second trace includes a first portion extending over the dielectric layer along a second longitudinal direction adjacent to the second opening, and a second portion disposed in the second opening and extending between the first portion of the second trace and the exposed portion of the conductive via, the second portion of the second trace has a maximum width along a second transverse direction orthogonal to the second longitudinal direction, and the maximum width of the second portion of the second trace is no greater than 3 times of a width of the first portion of the second trace.

12. The semiconductor device package of claim 10 , wherein the redistribution stack is a first redistribution stack, the semiconductor device package further comprises a second redistribution stack disposed over the back surface of the package body.

13. A semiconductor device package comprising:
a conductive post;
a package body encapsulating portions of the conductive post, wherein the package body includes a front surface and a back surface opposite to the front surface; and
a redistribution stack including
a dielectric layer disposed over the front surface of the package body and defining a first opening exposing at least a portion of a terminal end of the conductive post; and
an RDL disposed over the dielectric layer and including a first trace,
wherein the first trace includes a first portion extending over the dielectric layer, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the terminal end of the conductive post,
wherein a projection area of the first trace onto the terminal end of the conductive post is no greater than 15% of a total area of the terminal end of the conductive post.

14. The semiconductor device package of claim 13 , wherein the projection area of the first trace onto the terminal end of the conductive post is no greater than 10% of the total area of the terminal end of the conductive post.

15. The semiconductor device package of claim 13 , wherein the first portion of the first trace extends over the dielectric layer along a longitudinal direction adjacent to the first opening, the second portion of the first trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace.

16. The semiconductor device package of claim 15 , wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

17. The semiconductor device package of claim 13 , wherein the RDL further includes at least two additional traces extending over the dielectric layer and overlapping the terminal end of the conductive post disposed below the additional traces.

18. The semiconductor device package of claim 13 , further comprising an electronic device including an active surface and a contact pad adjacent to the active surface, wherein the conductive post extends between the contact pad of the electronic device and the front surface of the package body, and the package body encapsulates portions of the electronic device.

19. The semiconductor device package of claim 18 , wherein the electronic device is a first electronic device, the semiconductor device package further comprises a second electronic device, wherein the package body encapsulates portions of the second electronic device, and the RDL electrically connects the first electronic device to the second electronic device.

20. The semiconductor device package of claim 18 , wherein the condu

Assignees

• Advanced Semiconductor Eng

Inventors

• Hunt John Richard
• Chen William T
• Hung Chih-Pin
• Wang Chen-Chao

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title