Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
Wafer level semiconductor package and manufacturing methods thereof
US8941222B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941222-B2 |
| Application number | US-94469710-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 11, 2010 |
| Priority date | Nov 11, 2010 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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- Title
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Abstract
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A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor package, comprising: at least one semiconductor die having an active surface; an interposer element having an upper surface and a lower surface, the interposer element having at least one conductive via extending between the upper surface and the lower surface; a package body encapsulating portions of the semiconductor die and portions of the interposer element; and a lower redistribution layer that electrically connects the interposer…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8941222B2 cover?
- A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions…
- Who is the assignee on this patent?
- Hunt John Richard, Advanced Semiconductor Eng
- What technology area does this patent fall under?
- Primary CPC classification H10W74/473. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).