Power management integrated circuits and semiconductor memory modules including power management integrated circuits

Patent metadata

Field	Value
Publication number	US-10916274-B2
Application number	US-201916731908-A
Country	US
Kind code	B2
Filing date	Dec 31, 2019
Priority date	Apr 19, 2019
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.

First claim

What is claimed is:

1. A power management integrated circuit comprising:
first pads, second pads, a third pad, and a fourth pad configured to be connected with an external device;
a regulation block configured to receive first voltages from the first pads, to convert the first voltages to second voltages, and to output the second voltages to the second pads;
a communication block configured to receive a command through the third pad and to output an internal information request received together with the command responsive to the command; and
a logic block configured to control an operation of the regulation block, to receive the internal information request from the communication block, and to output internal state information to the fourth pad based on the internal information request.

2. The power management integrated circuit of claim 1 , wherein the internal state information comprises an internal voltage or current of the logic block.

3. The power management integrated circuit of claim 1 , wherein the logic block comprises a memory, and
wherein the internal state information comprises an operating voltage of an operation of the memory.

4. The power management integrated circuit of claim 3 , wherein the operating voltage comprises a multi-time program (MTP) voltage.

5. The power management integrated circuit of claim 1 , wherein the communication block is further configured to communicate with the external device through the third pad in compliance with an Inter-Integrated Circuit (I2C) and/or Improved Inter-Integrated Circuit (I3C) protocol.

6. The power management integrated circuit of claim 5 , wherein the communication block is further configured to output the internal information request received together with the command to the logic block responsive to the command having a predetermined format that differs from an I2C command of the I2C protocol and/or an I3C command of the I3C protocol.

7. The power management integrated circuit of claim 1 , wherein the internal information request comprises a first selection code for selecting a first internal state information of a plurality of internal state information of the logic block, and
wherein the logic block is further configured to output the first internal state information selected by the first selection code from among the plurality of internal state information to the fourth pad as the internal state information.

8. The power management integrated circuit of claim 7 , further comprising:
a fifth pad configured to be connected with the external device,
wherein the internal information request further comprises a second selection code for selecting a second internal state information of the plurality of internal state information of the logic block, and
wherein the logic block is further configured to output the second internal state information selected by the second selection code from among the plurality of internal state information to the fifth pad.

9. The power management integrated circuit of claim 7 , wherein the internal information request further comprises a latch out code, and
wherein the logic block is further configured to continue outputting the internal state information to the fourth pad in response to the latch out code.

10. The power management integrated circuit of claim 1 , wherein the fourth pad comprises two or more pads,
wherein the internal information request comprises two or more selection codes indicating two or more internal state information and a latch out code following the two or more selection codes,
wherein the logic block is further configured to output the two or more internal state information indicated by the two or more selection codes through the fourth pad in response to the latch out code, and
wherein the internal state information is included as one of the two or more internal state information.

11. The power management integrated circuit of claim 1 , wherein the internal information request comprises a restoration code, and
wherein the logic block is further configured to terminate outputting the internal state information to the fourth pad in response to the restoration code.

12. A semiconductor memory module comprising:
a printed circuit board comprising first connectors, second connectors, and third connectors configured to communicate with an external device;
memory devices on the printed circuit board, and configured to exchange a data signal and a data strobe signal with the external device through the first connectors;
a driver on the printed circuit board, and configured to receive a first command and an address from the external device through the second connectors and to control the memory devices in response to the first command and the address; and
a power management integrated circuit on the printed circuit board, and configured to receive first voltages from the external device through the third connectors, to convert the first voltages to second voltages, and to supply the second voltages to the memory devices and the driver,
wherein the power management integrated circuit is further configured to output an internal voltage or current responsive to a second command from the external device.

13. The semiconductor memory module of claim 12 , wherein the printed circuit board further comprises a fourth connector configured to communicate with the external device, and
wherein the second command is received through the fourth connector.

14. The semiconductor memory module of claim 12 , wherein the printed circuit board further comprises a fourth connector configured to communicate with the external device, and
wherein the driver is further configured to transfer the second command received through the fourth connector to the power management integrated circuit.

15. The semiconductor memory module of claim 12 , wherein the second command comprises a selection code, and
wherein the power management integrated circuit is further configured to select the internal voltage or current to output based on the selection code.

16. The semiconductor memory module of claim 12 , wherein the printed circuit board further comprises fourth connectors configured to communicate with the external device,
wherein the power management integrated circuit is further configured to transfer the internal voltage or current to the driver, and
wherein the driver is further configured to output, through the fourth connectors, the internal voltage or current that is transferred from the power management integrated circuit.

17. The semiconductor memory module of claim 12 , further comprising:
data buffers on the printed circuit board and corresponding to the memory devices, respectively,
wherein the memory devices are respectively connected with the first connectors through the data buffers.

18. The semiconductor memory module of claim 12 , wherein the power management integrated circuit is further configured to communicate with the external device in compliance with an Inter-Integrated Circuit (I2C) or Improved Inter-Integrated Circuit (I3C) protocol through a designated pad, and
wherein the second command is received through the designated pad and has a predetermined format that differs from an I2C command of the I2C protocol and/or an I3C command of the I3C protocol.

19. A power management integrated circuit comprising:
a first pad, a second pad, a third pad, a fourth pad, a fifth pad, a sixth pad, a seventh pad, an eighth pad, a ninth pad, a tenth pad, a data pad, and a clock pad configured to be connected with

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Geon
• Lee Kyudong
• Yun Jinseong

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title