Method of performing dynamic voltage and frequency scaling operation, application processor performing method, and mobile device comprising application processor

Patent metadata

Field	Value
Publication number	US-9541992-B2
Application number	US-201314022260-A
Country	US
Kind code	B2
Filing date	Sep 10, 2013
Priority date	Sep 10, 2012
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor, and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit.

First claim

What is claimed is:

1. A method of performing a dynamic voltage and frequency scaling operation, the method comprising:
controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor; and
controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit;
when the operating frequency information indicates an increase of the operating frequency of the application processor, controlling the CMU to increase the operating frequency of the application processor after controlling the PMIC to increase the operating voltage of the application processor; and
when the operating frequency information indicates a decrease of the operating frequency of the application processor, controlling the CMU to decrease the operating frequency of the application processor before controlling the PMIC to decrease the operating voltage of the application processor, wherein:
the operating frequency of the application processor corresponds to a frequency of a clock signal that is output from a clock generating unit, and the frequency of the clock signal is determined by the CMU,
the clock generating unit comprises multiple phase locked loops (PLLs), a multiplexer, and a frequency divider, and
the frequency of the clock signal is determined such that an output frequency of one output signal selected by the multiplexer among multiple output signals output from the PLLs is divided by the frequency divider.

2. The method of claim 1 , wherein the operating frequency of the application processor is changed by controlling the CMU to control the PLLs.

3. The method of claim 1 , wherein the operating frequency of the application processor is changed by controlling the CMU to control the frequency divider.

4. The method of claim 1 , wherein the operating frequency of the application processor is changed by controlling the CMU to control both the PLLs and the frequency divider.

5. The method of claim 1 , wherein the operating frequency of the application processor is changed by controlling the CMU to select one PLL among the PLLs.

6. The method of claim 1 , wherein the operating frequency of the application processor is changed by controlling the CMU to control the frequency divider.

7. The method of claim 1 , wherein the operating frequency of the application processor is changed by controlling the CMU to select one PLL among the PLLs, and to control the frequency divider.

8. An application processor comprising:
a central processing unit configured to operate based on a clock signal;
a clock generating unit configured to generate the clock signal; and
a clock management unit (CMU) configured to predict an operating state of the central processing unit, to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the central processing unit, and to change an operating frequency of the application processor based on the predicted operating state of the central processing unit, the operating frequency information indicating a change of the operating frequency of the application processor corresponding to a frequency of the clock signal, wherein:
an operating voltage of the application processor supplied by the PMIC is changed based on the operating frequency information,
the clock generating unit comprises multiple phase locked loops (PLLs), a multiplexer, and a frequency divider,
the frequency of the clock signal is determined such that an output frequency of one output signal selected by the multiplexer among multiple output signals output from the PLLs is divided by the frequency divider,
the CMU increases the operating frequency of the application processor after the PMIC increases the operating voltage of the application processor when the operating frequency information indicates an increase of the operating frequency of the application processor, and
the CMU decreases the operating frequency of the application processor before the PMIC decreases the operating voltage of the application processor when the operating frequency information indicates a decrease of the operating frequency of the application processor.

9. The application processor of claim 8 , wherein:
the CMU increases the operating frequency of the application processor by increasing the frequency of the one output signal using a first control signal indicating the increase of the operating frequency of the application processor to the PLLs, and
the CMU decreases the operating frequency of the application processor by decreasing the frequency of the one output signal using a second control signal indicating the decrease of the operating frequency of the application processor to the PLLs.

10. The application processor of claim 8 , wherein:
the CMU increases the operating frequency of the application processor by increasing the frequency of the clock signal using a first control signal indicating the increase of the operating frequency of the application processor to the frequency divider, and
the CMU decreases the operating frequency of the application processor by decreasing the frequency of the clock signal using a second control signal indicating the decrease of the operating frequency of the application processor to the frequency divider.

11. The application processor of claim 8 , wherein:
the CMU increases the operating frequency of the application processor by increasing the frequency of the one output signal using a first control signal indicating the increase of the operating frequency of the application processor to the PLLs, and by increasing the frequency of the clock signal using a third control signal indicating the increase of the operating frequency of the application processor to the frequency divider, and
the CMU decreases the operating frequency of the application processor by decreasing the frequency of the one output signal using a second control signal indicating the decrease of the operating frequency of the application processor to the PLLs, and by decreasing the frequency of the clock signal using a fourth control signal indicating the decrease of the operating frequency of the application processor to the frequency divider.

12. The application processor of claim 8 , wherein:
the CMU increases the operating frequency of the application processor by increasing the output frequencies of the output signals using a first control signal indicating the increase of the operating frequency of the application processor to the PLLs, and
the CMU decreases the operating frequency of the application processor by decreasing the output frequencies of the output signals using a second control signal indicating the decrease of the operating frequency of the application processor to the PLLs.

13. The application processor of claim 8 , wherein:
the CMU increases the operating frequency of the application processor by increasing the frequency of the clock signal using a first control signal indicating the increase of the operating frequency of the application processor to the frequency divider, and
the CMU decreases the operating frequency of the application processor by decreasing the frequency of the clock signal using a second control signal indicating the decrease of the operating frequency of the application processor to the frequency d

Assignees

• Lee Jae-Gon
• Shin Taek-Kyun
• Jeon Sang-Jung
• Choi Jin-Sub
• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Gon
• Shin Taek-Kyun
• Jeon Sang-Jung
• Choi Jin-Sub

Classifications

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• G06F1/324

  by lowering clock frequency · CPC title