Fan-out-semiconductor package module

Patent metadata

Field	Value
Publication number	US-10242973-B2
Application number	US-201815882440-A
Country	US
Kind code	B2
Filing date	Jan 29, 2018
Priority date	Jul 7, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A fan-out semiconductor package module includes: a core member having a first through hole and a second through hole; a semiconductor chip disposed in the first through hole, and having an active surface and an inactive surface opposite the active surface, the active surface having a connection pad disposed thereon; at least one first passive component disposed in the second through hole; a first encapsulant encapsulating the core member encapsulating at least a portion of each of the core member and the at least one first passive component; a second encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip; and a connection member disposed on the core member, the active surface of the semiconductor chip, and the at least one first passive component, and including a redistribution layer electrically connected to the connection pad and the at least one first passive component.

First claim

What is claimed is:

1. A fan-out semiconductor package module comprising:
a core member having a first through hole and a second through hole spaced from each other;
a semiconductor chip disposed in the first through hole, the semiconductor chip having an active surface and an inactive surface opposite the active surface, the active surface having a connection pad disposed thereon;
at least one first passive component disposed in the second through hole;
a first encapsulant encapsulating at least a portion of each of the core member and the at least one first passive component, the first encapsulant filling at least a portion of the second through hole;
a second encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip, the second encapsulant filling at least a portion of the first through hole; and
a connection member disposed on the core member, the active surface of the semiconductor chip, and the at least one first passive component, the connection member including a redistribution layer electrically connected to the connection pad and the at least one first passive component.

2. The fan-out semiconductor package module of claim 1 , further comprising: a metal layer disposed on a wall surface of the second through hole.

3. The fan-out semiconductor package module of claim 2 , wherein a wall surface of the first through hole is in physical contact with the second encapsulant.

4. The fan-out semiconductor package module of claim 2 , wherein the metal layer is connected to a ground included in the redistribution layer of the connection member.

5. The fan-out semiconductor package module of claim 2 , wherein the metal layer extends to an upper surface and a lower surface of the core member.

6. The fan-out semiconductor package module of claim 5 , further comprising:
a backside metal layer disposed on the first encapsulant or the second encapsulant; and
a backside via passing through at least a portion of the first encapsulant or the second encapsulant, the backside via connecting the metal layer to the backside metal layer.

7. The fan-out semiconductor package module of claim 5 , wherein the connection member includes a shielding structure surrounding the redistribution layer.

8. The fan-out semiconductor package module of claim 7 , wherein the shielding structure is connected to the metal layer.

9. The fan-out semiconductor package module of claim 1 , wherein the second encapsulant covers an upper surface of the first encapsulant.

10. The fan-out semiconductor package module of claim 1 , wherein respective upper surfaces of the first encapsulant and the second encapsulant are disposed on the same level.

11. The fan-out semiconductor package module of claim 1 , wherein the semiconductor chip and the at least one first passive component are disposed in parallel with each other, and are electrically connected to each other through the redistribution layer of the connection member.

12. The fan-out semiconductor package module of claim 11 , wherein the connection member further includes vias connecting the connection pad and the at least one first passive component to the redistribution layer of the connection member, and each of the connection pad and the at least one first passive component is in physical contact with the vias of the connection member.

13. The fan-out semiconductor package module of claim 1 , wherein the semiconductor chip includes a power management integrated circuit (PMIC), and the at least one first passive component includes a capacitor.

14. The fan-out semiconductor package module of claim 1 , wherein the core member further includes a third through hole spaced from the first through hole and from the second through hole, at least one second passive component is disposed in the third through hole, the first encapsulant encapsulates at least a portion of the at least one second passive component, and fills at least a portion of the third through hole, and the redistribution layer of the connection member is electrically connected to the at least one second passive component.

15. The fan-out semiconductor package module of claim 1 , further comprising: at least one third passive component disposed in the first through hole,
wherein the second encapsulant encapsulates at least a portion of the at least one third passive component, the redistribution layer of the connection member is electrically connected to the at least one third passive component, and a thickness of the at least one third passive component is greater than a thickness of the at least one first passive component.

16. The fan-out semiconductor package module of claim 1 , wherein the core member includes a wiring layer electrically connected to the connection pad and the at least one first passive component through the redistribution layer of the connection member.

17. The fan-out semiconductor package module of claim 16 , wherein the core member includes a first insulating layer contacting the connection member, a first wiring layer contacting the connection member and embedded in the first insulating layer, and a second wiring layer disposed on a second surface of the first insulating layer opposite a first surface of the first insulating layer, in which the first wiring layer is embedded, wherein the first wiring layer and the second wiring layer are electrically connected to the connection pad.

18. The fan-out semiconductor package module of claim 17 , wherein the core member further includes:
a second insulating layer disposed on the first insulating layer to cover the second wiring layer; and
a third wiring layer disposed on the second insulating layer, the third wiring layer being electrically connected to the connection pad.

19. The fan-out semiconductor package module of claim 1 , wherein the core member includes a first insulating layer, and a first wiring layer and the second wiring layer disposed on opposite surfaces of the first insulating layer, the first wiring layer and the second wiring layer being electrically connected to the connection pad.

20. The fan-out semiconductor package module of claim 19 , wherein the core member further includes:
a second insulating layer disposed on the first insulating layer to cover the first wiring layer;
a third wiring layer disposed on the second insulating layer;
a third insulating layer disposed on the first insulating layer to cover the second wiring layer; and
a fourth wiring layer disposed on the third insulating layer, the third wiring layer and the fourth wiring layer being electrically connected to the connection pad.

21. The fan-out semiconductor package module of claim 1 , wherein the first encapsulant and the second encapsulant have an interface therebetween.

22. The fan-out semiconductor package module of claim 1 , wherein the first encapsulant and the second encapsulant are made of different materials.

23. A semiconductor package module comprising:
a core member having a second through hole; a first passive component disposed in the second through hole;
a first encapsulant encapsulating at least a portion of each of the core member and the first passive component, the first encapsulant filling at least a portion of the second through hole;
a first through hole penetrating through the core member and the first encapsulant;
a semiconductor chip disposed in the first through hole, the semiconductor chip having an active surface and an inactive surface opposite

Assignees

• Samsung Electro Mech

Inventors

• Baek Yong Ho
• Jung Joo Hwan
• Hur Young Sik
• Gong Jung Chul
• Kim Han

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title