Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10903326-B2
Application number	US-201916246538-A
Country	US
Kind code	B2
Filing date	Jan 13, 2019
Priority date	Jan 13, 2019
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
forming a first gate structure on a substrate;
forming a second gate structure on one side of the first gate structure and covering a top surface of the first gate structure;
forming a third gate structure on another side of the first gate structure and covering the top surface of the first gate structure;
forming source/drain regions adjacent to the second gate structure and the third gate structure; and
forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions, wherein the contact plugs comprise:
a first contact plug directly contacting the first gate structure;
a second contact plug directly contacting the second gate structure; and
a third contact plug directly contacting the third gate structure, wherein a bottom surface of the first contact plug is lower than a bottom surface of the second contact plug and a bottom surface of the third contact plug.

2. The method of claim 1 , wherein the first gate structure comprises:
a first gate dielectric layer on the substrate; and
a first gate electrode on the first gate dielectric layer.

3. The method of claim 2 , further comprising:
forming a second gate dielectric layer on the substrate and the first gate structure;
forming a gate layer on the second gate dielectric layer; and
removing part of the gate layer and part of the second gate dielectric layer to form the second gate structure and the third gate structure.

4. The method of claim 3 , wherein the gate layer comprises polysilicon.

5. The method of claim 3 , wherein the second gate structure comprises:
a second gate electrode on one side of the first gate structure.

6. The method of claim 5 , wherein the second gate electrode comprises a first L-shape.

7. The method of claim 6 , wherein the first L-shape comprises a first vertical portion and a first horizontal portion and an edge of the first vertical portion is aligned with an edge of the second gate dielectric layer.

8. The method of claim 3 , wherein the third gate structure comprises:
a third gate electrode on another side of the first gate structure.

9. The method of claim 8 , wherein the third gate electrode comprises a second L-shape.

10. The method of claim 9 , wherein the second L-shape comprises a second vertical portion and a second horizontal portion and an edge of the second vertical portion is aligned with an edge of the second gate dielectric layer.

11. The method of claim 3 , further comprising:
forming a patterned mask on the gate layer;
forming a spacer around the patterned mask; and
using the patterned mask and the spacer to remove part of the gate layer and part of the second gate dielectric layer to form the second gate structure and the third gate structure.

12. The method of claim 3 , wherein the first gate dielectric layer and the second gate dielectric layer comprise different materials.

13. The method of claim 3 , wherein the first gate dielectric layer comprises silicon oxide.

14. The method of claim 3 , wherein the second gate dielectric layer comprises an oxide-nitride-oxide (ONO) layer.

15. A semiconductor device, comprising:
a first gate structure on a substrate;
a second gate structure on one side of the first gate structure and covering a top surface of the first gate structure;
a third gate structure on another side of the first gate structure and covering the top surface of the first gate structure;
source/drain regions adjacent to the second gate structure and the third gate structure; and
contact plugs contacting the first gate structure, the second gate structure, the third gate structure, and the source/drain regions, wherein the contact plugs comprise:
a first contact plug directly contacting the first gate structure;
a second contact plug directly contacting the second gate structure; and
a third contact plug directly contacting the third gate structure, wherein a bottom surface of the first contact plug is lower than a bottom surface of the second contact plug and a bottom surface of the third contact plug.

16. The semiconductor device of claim 15 , wherein the first gate structure comprises:
a first gate dielectric layer on the substrate; and
a first gate electrode on the first gate dielectric layer.

17. The semiconductor device of claim 16 , wherein the second gate structure comprises:
a second gate electrode on one side of the first gate structure.

18. The semiconductor device of claim 17 , further comprising a second gate dielectric layer between the second gate electrode and the first gate structure, wherein the second gate electrode comprises a first L-shape, the first L-shape comprises a first vertical portion and a first horizontal portion, and an edge of the first vertical portion is aligned with an edge of the second gate dielectric layer.

19. The semiconductor device of claim 16 , wherein the third gate structure comprises:
a third gate electrode on another side of the first gate structure.

20. The semiconductor device of claim 19 , further comprising a third gate dielectric layer between the third gate electrode and the first gate structure, wherein the second gate electrode comprises a second L-shape, the second L-shape comprises a second vertical portion and a second horizontal portion, and an edge of the second vertical portion is aligned with an edge of the third gate dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Huang Chun-Sung
• Wang Shen-De
• Hsu Chia-Ching
• Xiang Wang

Classifications

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/696 Primary

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H01L29/42344 Primary

  Electricity · mapped topic