Semiconductor packages and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9281260-B2
Application number	US-201213415556-A
Country	US
Kind code	B2
Filing date	Mar 8, 2012
Priority date	Mar 8, 2012
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package, the method comprising:
forming a die opening in a laminate substrate, the laminate substrate having a front side and a back side;
placing a die within the die opening; and
forming a spacer around the die, the spacer disposed between the laminate substrate and an outer sidewall of the die, the spacer partially extending over a portion of the die, the forming of the spacer including depositing a spacer material in a first region around a perimeter of the die, and removing a portion of the spacer material from the first region to form the spacer.

2. The method of claim 1 , wherein the laminate substrate has a upper conductive layer over the front side of the laminate substrate and a lower conductive layer under the back side of the laminate substrate, the method further comprising removing a portion of the upper and the lower conductive layers from the front side and the back side around the die opening.

3. The method of claim 1 , further comprising placing the laminate substrate on a carrier before placing the die within the die opening.

4. The method of claim 1 , further comprising:
coating a metallic material so as to cover the front side of the laminate substrate, a top surface of the spacer, and the top surface of the die;
forming a circuit layout comprising the metallic material coating and a thick conductive layer formed over the metallic material coating; and
forming a solder mask covering portions of the circuit layout.

5. The method of claim 1 , further comprising:
forming a through opening on the laminate substrate while forming the die opening; and
forming a through via with a metal by filling the through opening after forming the spacer.

6. A semiconductor package comprising:
a substrate having a first die opening;
a first die disposed within the first die opening; and
a first spacer disposed within a first gap between the laminate substrate and the first die, the first spacer disposed around a perimeter of the first die, the first spacer formed by depositing a spacer material in a first region around a perimeter of the first die, and removing a portion of the spacer material from the first region to form the first spacer.

7. The package of claim 6 , wherein the first spacer comprises an insulating material.

8. The package of claim 6 , further comprising:
a second die disposed within a second die opening within the substrate, the first die isolated from the second die by a portion of the substrate; and
a second spacer disposed within a second gap between the substrate and the second die, the second spacer disposed around a perimeter of the second die and having an “I” shaped structure.

9. A method, comprising:
providing a substrate with at least one opening having at least one substrate side surface;
depositing a die in the at least one opening, the die having at least one die side surface facing the at least one substrate side surface; and
forming at least one spacer between the at least one die side surface and the at least one substrate side surface, the forming of the at least one spacer including depositing a spacer material in a first region around a perimeter of the die, and removing a portion of the at least one spacer material from the first region to form the at least one spacer.

10. The method according to claim 9 , wherein the spacer contacts the at least one die side surface and the at least one substrate side surface.

11. The method according to claim 9 , wherein the substrate includes a substrate front surface and a substrate back surface, and the die includes a die front surface and a die back surface, the forming act further forms the at least one spacer over a portion of the substrate front surface and a portion of the die front surface.

12. The method according to claim 11 , wherein the forming act further forms the at least one spacer over a portion of the substrate back surface and the die back surface.

13. The method according to claim 11 , further comprising placing the substrate and the die, including the at least one spacer formed between the at least one die side surface and the at least one substrate side surface, over a carrier, the placing causing the at least one spacer to contact the carrier and further causing a gap to form between the substrate front surface and the carrier and between the die front surface and the carrier.

14. The method according to claim 11 , wherein the forming act further forms the at least one spacer over a portion of the substrate back surface and a portion of the die back surface.

15. An apparatus, comprising:
a substrate;
a die being adjacent the substrate; and
a spacer being placed between the die and the substrate, the spacer at least in contact with three surfaces of the substrate and being a contiguous structure formed by a curing process that integrates at least two portions of the spacer.

16. The apparatus according to claim 15 , wherein the spacer is further at least in contact with three surfaces of the die.

17. The apparatus according to claim 15 , wherein the spacer is in contact with side, front and bottom surfaces of the substrate, and further in contact with side, front and bottom surfaces of the die.

18. The apparatus according to claim 15 , wherein the substrate includes an opening, the die being positioned in the opening and the spacer being placed between a surface defining at least a portion of the opening and a lateral surface of the die.

19. A spacer to separate components, comprising:
a first recess to accommodate a first semiconductor component; and
a second recess to accommodate a second semiconductor component,
wherein the first recess is limited to protecting an edge of the first semiconductor component and the second recess is limited to protecting an edge of the second semiconductor.

20. The spacer according to claim 19 , wherein the spacer is formed from a polymer material.

21. The spacer according to claim 19 , wherein the spacer is formed from a thermally curable material.

22. The spacer according to claim 19 , wherein the first semiconductor component is a laminate substrate and the second semiconductor component is a die.

23. The spacer according to claim 19 , wherein the spacer has an “I” shape.

24. The spacer according to claim 19 , wherein the first recess is smaller than the second recess.

Assignees

• Standing Martin
• Roberts Andrew
• Infineon Technologies Ag

Inventors

• Standing Martin
• Roberts Andrew

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title