Apparatuses and methods involving adjustable circuit-stress test conditions for stressing regional circuits

Patent metadata

Field	Value
Publication number	US-10901023-B2
Application number	US-201816059547-A
Country	US
Kind code	B2
Filing date	Aug 9, 2018
Priority date	Aug 9, 2018
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

An example method includes stressing, under different circuit-stress test conditions, a plurality of different types of regional circuits susceptible to time dependent dielectric breakdown (TDDB), and in response, monitoring for levels of reliability failure associated with the plurality of different types of regional circuits. The method includes storing a set of stress-test data based on each of the levels of reliability failure, the set of stress-test data being stored within the integrated circuit to indicate reliability-threshold test data specific to the integrated circuit. Within the integrated circuit, an on-chip monitoring circuit indicates operational conditions of suspect reliability associated with dielectric breakdown of at least one of the plurality of different types of regional circuits. And, the method further includes, during operation of the integrated circuit, adjusting at least one of the different circuit-stress test conditions based on the indicated operational conditions of suspect reliability.

First claim

What is claimed is:

1. In an integrated circuit configured to indicate a reliability concern associated with the integrated circuit, a method comprising:
stressing, under different circuit-stress test conditions, a plurality of different types of regional circuits susceptible to time dependent dielectric breakdown (TDDB) respectively located in different regions of the integrated circuit, and which are used for monitoring levels of reliability failure associated with any of the plurality of different types of regional circuits;
determining and storing a set of stress-test data based on the levels of reliability failure of the plurality of different types of regional circuits, the set of stress-test data being stored within the integrated circuit to indicate reliability-threshold test data specific to the integrated circuit;
within the integrated circuit, detecting the levels of reliability failure of one or more of the plurality of different types of regional circuits via an on-chip monitoring circuit and indicating one or more operational conditions of suspect reliability associated with dielectric breakdown of at least one of the plurality of different types of regional circuits, wherein said at least one of the plurality of different types of regional circuits is different from one another of the plurality of different types of regional circuits in terms of manifesting respectively different overstress levels; and
providing logic circuitry in the integrated circuit which, during operation of said one or more of the plurality of different types of regional circuits in the integrated circuit, adjusts at least one of the different circuit-stress test conditions based on the indicated operational conditions of suspect reliability.

2. The method of claim 1 , wherein the different types of regional circuits include lifetime monitor circuits configured and arranged to monitor the integrated circuit for circuit failure related to TDDB, further including operating the integrated circuit under conditions which cause the logic circuitry in the integrated circuit to adjust the reliability-threshold test data based on the indicated operational conditions of suspect reliability.

3. The method of claim 1 , wherein stressing under different circuit-stress test conditions includes using activation circuits for overstressing the plurality of different types of regional circuits with respect to one or more of the following parameters: electrical-field strength or voltage level, temperature, electrical activity, and recovery period corresponding to a time span over which one or more of the plurality of the different types of regional circuits recovers, after being overstressed, to a previous state of operation or status.

4. The method of claim 1 , wherein the set of stress-test data corresponds to one or more criteria relating to mean time to failure (MTTF) due to a failure mechanism or MTTF due to TDDB.

5. The method of claim 1 , wherein the different circuit-stress test conditions include at least one circuit-stress test condition which occurs during operation of said one or more of the plurality of different types of regional circuits in the integrated circuit, and wherein the logic circuitry adjusts the reliability-threshold test data based on indicated operational conditions of suspect reliability failure detected responsive to applying the at least one adjusted different circuit-stress test condition which occurs during operation of said one or more of the plurality of different types of regional circuits in the integrated circuit.

6. The method of claim 1 , wherein the different circuit-stress test conditions include at least one circuit-stress test condition applied at a plurality of different times while operating the integrated circuit, and wherein the logic circuitry adjusts the at least one circuit-stress test condition based on the set of stress-test data.

7. The method of claim 1 , wherein the different circuit-stress test conditions cause: a first overstress effect associated with a first mean time to failure (MTTF) acceleration factor, a second overstress effect associated with a second MTTF acceleration factor which is lower than the first MTTF acceleration factor, and a third overstress effect associated with a third MTTF acceleration factor which is lower than the second MTTF acceleration factor.

8. The method of claim 1 , further including providing failure statistics based on the each of the levels of reliability failure of the plurality of different types of regional circuits, and wherein determining the set of stress-test data is based on the failure statistics.

9. The method of claim 1 , wherein the adjusted at least one of the different circuit-stress test conditions includes feedback data developed from the indicated operational conditions of suspect reliability.

10. The method of claim 1 , wherein the adjusted at least one of the different circuit-stress test conditions is based on feedback data including update data provided from a source external to the integrated circuit.

11. An apparatus comprising:
an integrated circuit including a plurality of different types of regional circuits susceptible to time dependent dielectric breakdown (TDDB) respectively located in different regions of the integrated circuit, wherein said at least one of the plurality of different types of regional circuits is different from one another of the plurality of different types of regional circuits in terms of manifesting respectively different overstress levels;
test circuitry to stress, the plurality of different types of regional circuits under different circuit-stress test conditions to enable levels of reliability failure associated with any of the plurality of different types of regional circuits to be detected in response;
processing circuitry to determine and store a set of stress-test data based on each of the levels of reliability failure of the plurality of different types of regional circuits, the set of stress-test data being stored within the integrated circuit to indicate reliability-threshold test data specific to the integrated circuit;
within the integrated circuit, an on-chip monitoring circuit to detect the levels of reliability failure associated with any of the plurality of different types regional circuits and to indicate operational conditions of suspect reliability of the plurality of different types of regional circuits based on the levels of reliability failure; and
logic circuitry within the integrated circuit and configured and arranged to, during operation of said one or more of the plurality of different types of regional circuits in the integrated circuit, adjust at least one of the circuit-stress test conditions based on the indicated operational conditions of suspect reliability.

12. The apparatus of claim 11 , wherein the plurality of different types of regional circuits comprise lifetime monitor circuits configured to monitor the integrated circuit for circuit failure, and wherein each of the plurality of different types of regional circuits include a plurality of sub-regional circuits that are susceptible to TDDB.

13. The apparatus claim 12 , wherein each of the sub-regional circuits are located at different locations of the integrated circuit, and the plurality of different types of regional circuits are to be overstressed with respect to the different circuit-stress test conditions including at least one of: a voltage, an electrical field strength, a temperature, an electrical activity, and a recovery period; and
wherein the logic circuitry to be apply the different circuit-stress test conditions and adjust the reliability-threshold test dat

Assignees

• Nxp Bv

Inventors

• Schat Jan-Peter
• Zanati Abdellatif

Classifications

• G01R31/18

  Subjecting similar articles in turn to test, e.g. go/no-go tests in mass production · CPC title

• G01R31/2874

  related to temperature · CPC title

• G01R31/14 Primary

  Circuits therefor {, e.g. for generating test voltages, sensing circuits (G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327)} · CPC title

• G01R31/2858

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title

• G01R31/3004

  Current or voltage test · CPC title