Monitoring aging of silicon in an integrated circuit device

Patent metadata

Field	Value
Publication number	US-9310424-B2
Application number	US-201313775502-A
Country	US
Kind code	B2
Filing date	Feb 25, 2013
Priority date	Feb 25, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.

First claim

What is claimed is:

1. A method, in a data processing system, for determining a modeled age of a multi-core processor, the method comprising:
for each core in a set of cores in the multi-core processor executing in the data processing system, determining, by age determination logic executing in the data processing system, a temperature via temperature monitoring logic, a voltage via voltage monitoring logic, and a frequency via frequency monitoring logic at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor, wherein the temperature, the voltage, and the frequency are measurements of run-time operational characteristics experienced by each core of the set of cores and wherein forming the modeled age of the multi-core processor comprises:
for each degradation in the set of degradations, each voltage domain in the set of voltage domains, and each core in the set of cores, computing, by the age determination logic, a time at a reference condition (t ref ) value utilizing the determined temperature, voltage, and frequency of the current interval; and
increasing, by the age determination logic, a current value for the modeled age of the multi-core processor by the t ref value;

determining, by the age determination logic, whether the modeled age of the multi-core processor is greater than an end-of-life value; and
responsive to the modeled age of the multi-core processor being greater than end-of-life value, sending, by the age determination logic, an indication that the multi-core processor requires replacement.

2. The method of claim 1 , further comprising:
responsive to the modeled age of the multi-core processor being less than or equal to the end-of-life value, repeating, by the age determination logic, the process to calculate a new modeled age of the multi-core processor; and
determining, by the age determination logic, whether the new modeled age of the multi-core processor is greater than an end-of-life value.

3. The method of claim 1 , wherein the t ref value is computed utilizing, a negative bias temperature instability (NBTI) or positive bias temperature instability (PBTI) degradation equation, a time dependent dielectric breakdown (TDDB) degradation equation, or a PCCA (gate and contact) time dependent dielectric breakdown (TDDB) degradation equation.

4. The method of claim 1 , wherein the set of degradations comprise at least two from a negative bias temperature instability (NBTI), a positive bias temperature instability (PBTI), hot carrier injection (HCI), a stress induced leakage current (SILC), or a time dependent dielectric breakdown (TDDB).

5. The method of claim 1 , wherein the set of voltage domains comprises at least two different voltage domains.

6. The method of claim 1 , wherein the set of cores is at least two cores.

7. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
for each core in a set of cores in the multi-core processor executing in the computing device, determine, by age determination logic executing in the data processing system, a temperature via temperature monitoring logic, a voltage via voltage monitoring logic, and a frequency via frequency monitoring logic at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor, wherein the temperature, the voltage, and the frequency are measurements of run-time operational characteristics experienced by each core of the set of cores and wherein the computer readable program to form the modeled age of the multi-core processor further causes the computing device to:
for each degradation in the set of degradations, each voltage domain in the set of voltage domains, and each core in the set of cores, compute, by the age determination logic, a time at a reference condition (t ref ) value utilizing the determined temperature, voltage, and frequency of the current interval; and
increase, by the age determination logic, a current value for the modeled age of the multi-core processor by the t ref value;

determine, by the age determination logic, whether the modeled age of the multi-core processor is greater than an end-of-life value; and
responsive to the modeled age of the multi-core processor being greater than an end-of-life value, send, by the determination logic, an indication that the multi-core processor requires replacement.

8. The computer program product of claim 7 , wherein the computer readable program further causes the computing device to:
responsive to the modeled age of the multi-core processor being less than or equal to the end-of-life value, repeat, by the age determination logic, the process to calculate a new modeled age of the multi-core processor; and
determine, by the age determination logic, whether the new modeled age of the multi-core processor is greater than an end-of-life value.

9. The computer program product of claim 7 , wherein the t ref value is computed utilizing, a negative bias temperature instability (NBTI) or positive bias temperature instability (PBTI) degradation equation, a time dependent dielectric breakdown (TDDB) degradation equation, or a PCCA (gate and contact) time dependent dielectric breakdown (TDDB) degradation equation.

10. The computer program product of claim 7 , wherein the set of degradations comprise at least two from a negative bias temperature instability (NBTI), a positive bias temperature instability (PBTI), hot carrier injection (HCI), a stress induced leakage current (SILC), or a time dependent dielectric breakdown (TDDB).

11. The computer program product of claim 7 , wherein the set of voltage domains comprises at least two different voltage domains.

12. The computer program product of claim 7 , wherein the set of cores is at least two cores.

13. An apparatus, comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
for each core in a set of cores in the multi-core processor executing in the apparatus, determine, by age determination logic executing in the data processing system, a temperature via temperature monitoring logic, a voltage via voltage monitoring logic, and a frequency via frequency monitoring logic at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor, wherein the temperature, the voltage, and the frequency are measurements of run-time operational characteristics experienced by each core of the set of cores and wherein the instructions to form the modeled age of the multi-core processor further cause the processor to:
for each degradation in the set of degradations, each voltage domain in the set of voltage domains, and each core in the set of cores, compute, by the age determination logic, a time at a reference condition (t ref ) value utilizing the determined temperature, voltage, and frequency of the current interval; and
increase, by the age determination logic, a current value for the modeled age of the multi-core processor by the t ref value;

determine, by the age determination logic, whether the modeled age of the multi-core processor is greater than an end-of-life value; and
responsive to the modeled age of the multi-core processor being greater than an end-of-life value, send, by the age determination logic, an indication that the multi-core processor requires r

Assignees

• IBM

Inventors

• Allen-Ware Malcolm S
• Bolam Ronald J
• Drake Alan J
• Lefurgy Charles R
• Linder Barry P
• Mittl Steven W
• Rajamani Karthick

Classifications

• G01R31/2851 Primary

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title